A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. A 2D material layer is formed over the dielectric layer. An adhesion layer is formed over the 2D material layer. Source/drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed over the adhesion layer, wherein the adhesion layer has a material different from a material of the first high-k gate dielectric layer.

A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

A method of fabricating a semiconductor device includes providing an engineered substrate. The method further includes forming an epitaxial gallium nitride (GaN) layer coupled to the engineered substrate, forming a plurality of trenches in the epitaxial GaN layer, and forming a plurality of gates in the trenches. The method further includes forming a plurality of sources coupled to the epitaxial GaN layer, forming an interconnect structure on the gates and sources, forming a metal bonding layer on the interconnect structure, bonding a conductive carrier to the metal bonding layer, removing the engineered substrate, forming a drain layer on the back surface of the epitaxial GaN layer, etching at least one portion of the epitaxial GaN layer and the interconnect structure to form at least one gate pad recess and expose the embedded metal track; and forming at least one gate electrode in the gate pad recess.

A semiconductor device includes a graphene film disposed on a substrate and formed of atomic layers of graphene that are stacked, a source electrode and a drain electrode disposed on the graphene film, and a gate electrode disposed on the graphene film between the source electrode and the drain electrode with a gate insulator film interposed between the gate electrode and the graphene film, wherein a first number of the atomic layers of the graphene film in a source region where the source electrode is located and a drain region where the drain electrode is located is greater than a second number of the atomic layers of the graphene film in a channel region where the gate electrode is located.

A semiconductor device includes a first transistor, a first via contact, a second transistor and a second via contact. The first transistor includes a channel and a gate electrode. The first via contact is disposed on the gate electrode of the first transistor, and corresponds in position to the channel of the first transistor. The second transistor includes a channel and a gate electrode. The second via contact is disposed on the gate electrode of the second transistor, and corresponds in position to the channel of the second transistor. A distance between the second via contact and the channel of the second transistor is smaller than a distance between the first via contact and the channel of the first transistor.

A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

A transistor includes a vertical stack containing, in order from bottom to top or from top to bottom, a gate electrode, a gate dielectric, and an active layer and located over a substrate. The active layer includes an amorphous semiconductor material. A crystalline source region including a first portion of a crystalline semiconductor material overlies, and is electrically connected to, a first end portion of the active layer. A crystalline drain region including a second portion of the crystalline semiconductor material overlies, and is electrically connected to, a second end portion of the active layer.

A gate electrode includes a main portion formed of a gate electrode material, and a gate electrode barrier layer disposed between the main portion and a barrier layer and formed of a conductive material that prevents the gate electrode material from diffusing into the barrier layer. A surface of the main portion in a region above a first insulating layer faces a periphery without a layer of the conductive material being formed.

A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.

Provided is a metal-oxide thin-film transistor. The metal-oxide thin-film transistor includes a gate, a gate insulation layer, a metal-oxide semiconductor layer, a source electrode, a drain electrode, and a passivation layer that are successively disposed on a base substrate; wherein the source electrode and the drain electrode are both in a laminated structure, wherein the laminated structure of the source electrode or the drain electrode at least includes a bulk metal layer and an electrode protection layer; wherein the electrode protection layer includes a metal or a metal alloy; the electrode protection layer is at least disposed between the metal-oxide semiconductor layer and the bulk metal layer; wherein a metal-oxide layer is disposed between the electrode protection layer and the bulk metal layer.