Patent classifications
H10D48/385
Homoepitaxial tunnel barriers with functionalized graphene-on-graphene and methods of making
This disclosure describes a method of making a tunnel barrier-based electronic device, in which the tunnel barrier and transport channel are made of the same materialgraphene. A homoepitaxial tunnel barrier/transport device is created using a monolayer chemically modified graphene sheet as a tunnel barrier on another monolayer graphene sheet. This device displays enhanced spintronic properties over heteroepitaxial devices and is the first to use graphene as both the tunnel barrier and channel.
Coherent spin field effect transistor
A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000 K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co.sub.3O.sub.4 (111). Other magnetic materials and oxides may be employed. A few ML field of graphene is deposited on the cobalt (III) oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.
DATA READER WITH SPIN FILTER
A data reader may be configured with at least a detector stack positioned on an air bearing surface and consisting of a spin accumulation channel continuously extending from the air bearing surface to an injector stack. The injector stack can have at least one cladding layer contacting the spin accumulation channel. The at least one cladding layer may have a length as measured perpendicular to the ABS that filters minority spins from the detector stack.
Magnetic tunnel junction (MTJ) memory element having tri-layer perpendicular reference layer
The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure in between a seed layer and a cap layer. The MTJ structure includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; and a magnetic fixed layer separated from the magnetic reference layer structure by an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by an intermediate magnetic reference layer. The first, second, and intermediate magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction that is opposite to the first invariable magnetization direction.
Thermoelectric conversion element and manufacturing method for the same
Concerning a thermoelectric conversion element, it is desired to provide a new spin current to charge current conversion material. A thermoelectric conversion element includes a magnetic layer possessing in-plane magnetization, and an electromotive layer magnetically coupled to the magnetic layer. The electromotive layer is formed of a carbon material, possesses anisotropy of electric conductivity, and further includes an additive.
MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR ENHANCEMENT LAYER
The present invention is directed to an MTJ memory element comprising a magnetic free layer structure including one or more magnetic free layers that have a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure including a first magnetic reference layer and a second magnetic reference layer with a perpendicular enhancement layer interposed therebetween, the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The non-magnetic perpendicular enhancement layer includes a first perpendicular enhancement sublayer formed adjacent to the first magnetic reference layer and a second perpendicular enhancement sublayer formed adjacent to the second magnetic reference layer.
Spin wave device and logic circuit using spin wave device
As a technique for attaining a reduction in power consumption, there is a technique for reducing power consumption using a spin wave. No specific proposal concerning spin wave generation, spin wave detection, and a latch technique for information has been made. A device applies an electric field to a first electrode of a nonmagnetic material using a thin line-shaped stacked body including a first ferromagnetic layer and a nonmagnetic layer to thereby generate a spin wave in the first ferromagnetic layer, and detects a phase or amplitude of the spin wave propagated in the first ferromagnetic layer using a second electrode of a ferromagnetic material with a magnetoresistance effect.
GRAPHENE FLUORINATION FOR INTEGRATION OF GRAPHENE WITH INSULATORS AND DEVICES
Embodiments of the present disclosure describe multi-layer graphene assemblies including a layer of fluorinated graphene, dies and systems containing such structures, as well as methods of fabrication. The fluorinated graphene provides an insulating interface to other graphene layers while maintaining the desirable characteristics of the nonfluorinated graphene layers. The assemblies provide new options for utilizing graphene in integrated circuit devices and interfacing graphene with other materials. Other embodiments may be described and/or claimed.
MONOLITHIC QUBIT INTEGRATED CIRCUITS
Described is a monolithic integrated circuit for use in quantum computing based on single and multiple coupled quantum dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in commercial complementary metal-oxide-semiconductor (CMOS) technology. The integrated circuit includes a plurality of n-channel or p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes each including a single-spin qubit or two coupled quantum dot qubits formed in an undoped semiconductor film adjacent at least one top gate. There is also a back gate formed in a silicon substrate adjacent a buried oxide layer or the at least one top gate, where the back gate controls the electron or hole entanglement and exchange interaction between the two coupled quantum dot qubits. The monolithic integrated circuits described may be used for monolithically integrated semiconductor quantum processors for quantum information processing.
Magnetic state element and circuits
Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.