A system-on-chip includes a substrate, a plurality of unit cells on the substrate, a first power mesh, and a second power mesh. The first power mesh includes a power rail that is connected to power terminals of the plurality of unit cells and is provided in a first metallization layer. The first power mesh also includes a power strap in a second metallization layer. The second power mesh is provided in a third metallization layer and a fourth metallization layer.

A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.

A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.

The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.

Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is not connected to any power rail.

A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.

A semiconductor structure includes a plurality of cells. Each cell has a plurality of transistors, a plurality of inner metal lines, two first backside power lines and one second backside power line. The inner metal lines, the first backside power lines and the second backside power line are disposed on a back side of the transistors. The inner metal lines, the first backside power lines and the second backside power line extend along a first axis. The second backside power line is disposed between the two first backside power lines. The inner metal lines are electrically connected to the first backside power lines and the transistors, and electrically connected to the second backside power line and the transistors. The cells are arranged along a second axis, the second axis being vertical to the first axis.

A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.

An integrated circuit (IC) comprises first and second conductors in one layer of the IC, wherein the first conductor is oriented along a first direction, the second conductor is oriented along a second direction generally perpendicular to the first direction, and the second conductor is electrically connected to the first conductor. The IC further comprises a third conductor in another layer of the IC, oriented along the second direction, and above the second conductor; a first via connecting the first and third conductors; and a second via connecting the second and third conductors.