Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

A transistor device includes an individual transistor cell arranged in a transistor cell field on a semiconductor body, the individual transistor cell having a gate electrode. The transistor device further includes a gate contact, electrically coupled to the gate electrode and configured to switch on the individual transistor cell by providing a gate current in a first direction and configured to switch off the individual transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction. The transistor device also includes a gate-resistor structure monolithically integrated in the transistor device. The gate-resistor structure provides a first resistance for the gate current when the gate current flows in the first direction, and provides a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Provided is a semiconductor device in which deterioration of a gate insulating layer is suppressed. A semiconductor device includes a semiconductor substrate, a gate insulating film, a gate electrode, a first electric wire, and a semiconductive insulating layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the semiconductor substrate with the gate insulating film being interposed therebetween. The first electric wire is connected to the gate electrode. The semiconductive insulating layer is connected to at least one of the gate electrode and the first electric wire.

A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

A semiconductor device includes a semiconductor layer. The entire length of an outer peripheral side among outer peripheral sides of a first gate electrode region and the entire length of an outer peripheral side among outer peripheral sides of a first resistance element region match a portion of an outer peripheral side, among outer peripheral sides of the semiconductor layer, that is orthogonal to a border line and has the shortest distance to a first gate pad. Among four corner portions of an outer periphery of the first gate electrode region, only one corner portion is included in the outer peripheral sides of the first resistance element region, the only one corner portion having the shortest distance to the border line and the shortest distance to an outer peripheral side, among the outer peripheral sides of the semiconductor layer, that is orthogonal to the border line.

A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

A semiconductor device and a manufacturing method thereof are in the present invention. The semiconductor device includes a substrate, a source structure, a semiconductor structure, a gate structure, and a doped semiconductor layer. The source structure is disposed on the substrate. The semiconductor structure is disposed above the source structure. The gate structure is disposed above the source structure and surrounds the semiconductor structure. The doped semiconductor layer is disposed between the source structure and the semiconductor structure. Accordingly, the operation performance of the semiconductor device may be improved.

Semiconductor devices comprise a semiconductor layer structure and a gate structure that comprises a high resistance portion and a low-resistance portion on the semiconductor layer structure. The high resistance portion of the gate structure comprises a first section that has a first resistance temperature coefficient and a second section that has a second resistance temperature coefficient that differs from the first resistance temperature coefficient.