An organic light emitting display device is discussed. The organic light emitting display device according to an embodiment includes a base substrate, a buffer layer disposed on the base substrate, and a thin film transistor disposed on the buffer layer. The organic light emitting display device further includes an organic light emitting diode connected to the thin film transistor and disposed on the thin film transistor. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode. At least one of the gate, source, and drain electrodes of the thin film transistor includes a semi-transmissive metal layer, a transparent metal layer, and a reflective metal layer to improve outdoor visibility of a display panel by reducing reflectance of the electrodes even though a polarizer is removed.

A transparent electrode including: a first layer including a thermosetting copolymer including a first repeating unit having an aromatic moiety as a pendant group or incorporated in a backbone of the copolymer and a second repeating unit capable of lowering a curing temperature, a combination of a first polymer including the first repeating unit and a second polymer including the second repeating unit, or a combination thereof; a second layer disposed directly on one side of the first layer, wherein the second layer includes graphene; and a third layer disposed on the second layer, wherein the third layer includes an electrically conductive metal nanowire.

According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.

A semiconductor device includes a substrate, a back-barrier layer, a channel layer that has a band gap smaller than a band gap of the back-barrier layer, a first barrier layer that has a band gap larger than the band gap of the channel layer, a second barrier layer that is provided to fill a first recessed portion and has a band gap larger than the band gap of the channel layer, a source electrode, a drain electrode, and a gate electrode. An In composition ratio of the first barrier layer is greater than or equal to 0 and less than an In composition ratio of the second barrier layer. An Al composition ratio of the first barrier layer is greater than or equal to an Al composition ratio of the second barrier layer.

A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.

A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

In some embodiments, an integrated chip is provided. The integrated chip includes a source region and a drain region disposed in a substrate. A gate is disposed over the substrate and between the source region and the drain region. A silicide structure is disposed over the drain region. A first silicide blocking segment and a second silicide blocking segment are disposed directly over the drain region. The silicide structure continuously extends over the drain region from a first sidewall contacting the first silicide blocking segment to a second sidewall contacting the second silicide blocking segment, in a cross-sectional view.