Patent classifications
H10F39/80377
LIGHT DETECTION DEVICE
A light detection device includes: a TFT having a semiconductor layer supported on a substrate, a source electrode, a drain electrode, and a gate electrode; a photodiode having a bottom electrode electrically connected to the drain electrode, a semiconductor laminate structure, and a top electrode; and an electrode made of the same conductive film as the bottom electrode and arranged on the semiconductor layer with an insulating layer interposed therebetween.
SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device which enables data compression with a small amount of data. The present invention is a semiconductor device which includes a pixel portion, a memory, a first circuit, and a second circuit. The pixel portion has a function of obtaining imaging data. The first circuit has a function of performing discrete cosine transform on the imaging data, and generating first data. The first data is analog data, and the memory has a function of retaining the first data. The second circuit has a function of performing discrete cosine transform on the first data, and generating second data. The memory includes a first transistor, which includes an oxide semiconductor in a channel formation region, and a second transistor, in which a channel formation region is provided in a Si wafer.
SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
A small semiconductor device suitable for high-speed operation is provided. The semiconductor device includes a first circuit, a global bit line pair for writing, a global bit line pair for reading, and a local bit line pair. The first circuit includes second to fifth circuits. The second to fifth circuits are electrically connected to each other by the local bit line pair. The second circuit functions as a read/write selection switch. The third circuit functions as a working memory that stores 1-bit complementary data temporarily. The fourth circuit has a function of precharging the local bit line pair. The fifth circuit includes n (n is an integer of 2 or more) sixth circuits. The sixth circuits each have a function of retaining 1-bit complementary data written from the third circuit.
Method for manufacturing semiconductor device
In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
Solid-state image sensor, method of manufacturing the same, and camera
A solid-state image sensor includes a pixel area and a peripheral circuit area. The pixel area includes a first MOS, and the peripheral circuit area includes a second MOS. A method includes forming a gate of the first MOS and a gate of the second MOS, forming a first insulating film to cover the gates of the first and second MOSs, etching the first insulating film in the peripheral circuit area in a state that the pixel area is masked to form a side spacer on a side face of the gate of the second MOS, etching the first insulating film in the pixel area in a state that the peripheral circuit area is masked, and forming the second insulating film to cover the gates of the first and second MOSs and the side spacers.
SEMICONDUCTOR PHOTOSENSITIVE UNIT AND SEMICONDUCTOR PHOTOSENSITIVE UNIT ARRAY THEREOF
The present invention relates to a semiconductor photosensitive unit and a semiconductor photosensitive unit array thereof, including a floating gate transistor, a gating MOS transistor and a photodiode that are disposed on a semiconductor substrate. An anode or a cathode of the photodiode is connected to a floating gate of the floating gate transistor through the gating MOS transistor, and the corresponding cathode or anode of the photodiode is connected to a drain of the floating gate transistor or connected to an external electrode. After the gating MOS transistor is switched on, the floating gate is charged or discharged through the photodiode; and after the gating MOS transistor is switched off, charges are stored in the floating gate of the floating gate transistor. Advantages like a small unit area, low surface noise, long charge storage time of the floating gate, and large dynamic range of an operating voltage are achieved.
IMAGING DEVICE, MODULE, ELECTRONIC DEVICE, AND METHOD OF OPERATING THE IMAGING DEVICE
An imaging device that has a structure where a transistor is used in common by a plurality of pixels and is capable of imaging with a global shutter system is provided. A transistor that resets the potential of a charge detection portion, a transistor that outputs a signal corresponding to the potential of the charge detection portion, and a transistor that selects a pixel are used in common by the plurality of pixels. A node AN (a first charge retention portion), a node FD (a second charge retention portion), and a node FDX (the charge detection portion) are provided. Imaging data obtained in the node AN is transferred to the node FD, and the imaging data is sequentially transferred from the node FD to the node FDX to be read.
HIGH DYNAMIC RANGE AND GLOBAL SHUTTER IMAGE SENSOR PIXELS HAVING CHARGE OVERFLOW SIGNAL DETECTING STRUCTURES
An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.
Semiconductor device and method for fabricating the same
The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
Semiconductor device and solid-state imaging sensor
A semiconductor device according to an aspect of the present technology includes a low-concentration N-type region, a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction, which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked, a first insulating film placed between the gate electrode and the low-concentration N-type region, and a second insulating film placed between the gate electrode and the first high-concentration N-type region. The first high-concentration N-type region is connected to one of a source electrode and a drain electrode. The second high-concentration N-type region is connected to the other of the source electrode and the drain electrode.