A semiconductor device capable of achieving both short channel suppression and suppression of variations in transistor characteristics that includes a semiconductor substrate and a field-effect transistor on the semiconductor substrate. The field-effect transistor includes a diffusion layer region in which a channel is formed, a gate electrode covering at least a part of the diffusion layer region and having a side wall facing a side surface of the diffusion layer region and a top plate facing an upper surface of the diffusion layer region, a source region connected to one side of the gate electrode, and a drain region connected to the other side of the gate electrode portion. The side wall and the top plate of the gate electrode have a self-aligned structure. The source region and the drain region are formed to be self-aligned by implanting impurities obliquely into the side wall portion of the gate electrode portion.

A pixel transistor is disposed in a trench that isolates a pixel of a solid-state imaging device. The solid-state imaging device includes the trench and the pixel transistor. The trench isolates the pixel. The pixel transistor forms a channel region in a direction intersecting the depth direction of the trench along the side surface of the trench. At least a part of a gate electrode of the pixel transistor may be located in the trench. At least one of a source, a drain, or a floating diffusion of the pixel transistor may be located on the side surface of the trench. The pixel transistor may include at least one of a drive transistor, a selection transistor, a reset transistor, or a transfer transistor.

In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.

A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

A sensing device includes a light source to emit light, a light sensor to detect reflection of the emitted light and distance determination circuitry responsive to reflected-light detection within the light sensor. The light sensor includes a photodetector having a photocharge storage capacity in excess of one electron and an output circuit that generates an output signal responsive to light detection within the photodetector with sub-hundred nanosecond latency. The distance determination circuitry measures an elapsed time based on transition of the output signal in response to photonic detection within the photodetector and determines, based on the elapsed time, a distance between the sensing device and a surface that yielded the reflection of the emitted light.

The phenomenon of charge trapping and its impact on noise performance of an imaging array using thin film transistor switches can be ameliorated by compensation techniques. One such compensation technique is a recovery process by which trapped charges are detrapped through the periodic imposition of thermal, optical, and/or bias energy. Another technique involves a shield line overlying the transistor switches and connected to the gate base to reduce the gate base resistance and hence reduce changes in the RC time constant of the gate bus.

An imaging device suitable for detecting infrared light is provided. The imaging device includes a first layer, a second layer, a third layer, and a fourth layer, which are stacked in this order. The first layer includes an infrared-light-transmitting filter. The second layer includes single crystal silicon. The third layer includes a device-formation layer. The fourth layer includes a support substrate. The second layer includes a photoelectric-conversion device whose light-absorption layer is the single crystal silicon. The third layer includes a transistor which includes a metal oxide in its channel formation region. The photoelectric-conversion device and the transistor are electrically connected. The photoelectric-conversion device receives light which has passed through the infrared-light-transmitting filter.

There is provided an imaging device and a semiconductor device capable of suppressing deterioration of characteristics of pixel transistors (alternatively, transistors) provided in a second semiconductor layer due to electromagnetic interference from a first semiconductor layer side. An imaging device includes a first semiconductor layer provided with a sensor pixel that performs photoelectric conversion, a second semiconductor layer disposed on one surface side of the first semiconductor layer and provided with a pixel transistor for outputting a pixel signal based on a charge output from the sensor pixel, an insulating layer disposed between the first semiconductor layer and the second semiconductor layer, and a conductor layer disposed between the sensor pixel and the pixel transistor in the insulating layer. A potential of the conductor layer is fixed to a reference potential.

An image sensing device includes: a substrate; and a plurality of pixels isolated by an insulating film disposed within the semiconductor substrate. The plurality of pixels share a first active region, wherein at least one of the plurality of pixels comprises a photoelectronic conversion element and a transfer transistor. The photoelectronic conversion element is connected to the first active region by the transfer transistor. The first active region and a first floating diffusion region are connected by the transfer transistor. The first floating diffusion region is connected to a gate of a source follower transistor, and the first floating diffusion region is connected to a second floating diffusion region through a first transistor. The first transistor is turned off when an operating mode is a first mode. The first transistor is turned on when the operating mode is a second mode different from the first mode.

A semiconductor device with a small circuit scale is provided. The semiconductor device includes a first circuit and a second circuit. The first circuit includes first to n-th (n is an integer of 2 or more) transistors and the second circuit includes (n+1)-th to 2n-th transistors. The first to n-th transistors are connected in parallel to each other and the (n+1)-th to 2n-th transistors are connected in series to each other. First to n-th signals are supplied to the first circuit and the second circuit. The first circuit has a function of outputting a first potential when each of potentials of the first to n-th signals is lower than or equal to a first reference potential, and outputting a second potential when at least one of the potentials of the first to n-th signals is higher than the first reference potential. The second circuit has a function of outputting a third potential when each of the potentials of the first to n-th signals is higher than a second reference potential, and outputting the first potential when at least one of the potentials of the first to n-th signals is lower than or equal to the second reference potential.