In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

An image sensor is provided and may include a semiconductor substrate having a surface and including a trench, the trench extending from the surface into the semiconductor substrate, an insulating pattern provided in the trench; and a doped region in the semiconductor substrate and on the insulating pattern. The doped region includes a side portion on a side surface of the insulating pattern, and a bottom portion on a bottom surface of the insulating pattern. A thickness of the side portion of the doped region is from 85% to 115% of a thickness of the bottom portion of the doped region, and a number of dopants per unit area in the side portion of the doped region is from 85% to 115% of a number of dopants per unit area in the bottom portion.

When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 110.sup.13 atoms/cm.sup.2 or lower.

A semiconductor device includes an active matrix, using Indium Gallium Zinc Oxide (IGZO) as a semiconductor layer, wherein the IGZO is patterned to create distinct conductive and semiconductive regions across the active matrix, and wherein the semiconductor device comprises an IGZO TFT.

An image sensing device may include a photoelectric conversion region structured to convert incident light into photocharge, a first transmission gate structured to transfer the photocharge generated by the photoelectric conversion region to a first floating diffusion region structured to store the photocharge, and a second transmission gate structured to transfer the photocharge transferred to the first floating diffusion region to a second floating diffusion region structured to store the photocharge for readout, wherein a first side surface of the second transmission gate abuts on a side surface of the first transmission gate, the first floating diffusion region abuts on a bottom surface of the second transmission gate and the side surface of the first transmission gate, and the second floating diffusion region abuts on a second side surface of the second transmission gate facing away from the first side surface of the second transmission gate.

A purpose of the present invention is to countermeasure a connection failure of an electrode in an optical sensor using PIN type photo conductive film. A structure of the present invention is as follows. A semiconductor device including an optical sensor, the optical sensor including: a thin film transistor formed on a substrate, and a photo diode formed above the thin film transistor, in which the photo diode includes an anode, a photo conductive film and a cathode, the cathode is constituted from a titanium film, and a first transparent conductive film is formed between the titanium film and the photo conductive film.

An image sensor pixel array includes a source follower transistor configured with an asymmetric doping profile under its gate. In an example, a given pixel of a pixel array includes a photodetector coupled to a readout circuit, which includes a transfer gate between the photodetector and a source follower transistor. In an example, the source follower transistor includes doped source and drain regions with a lightly doped drain (LDD) region adjacent to the source region, but no corresponding LDD region adjacent to the drain region. Such a configuration allows for reduced parasitic capacitance across the gate-drain junction of the transistor, which provides a higher conversion gain for the pixel.

An image sensing device includes a pixel array of a plurality of unit pixels arranged in a row direction and a column direction and including a first unit pixel that includes floating diffusion region configured to store photocharge generated within the first unit pixel in corresponding to incident light; a first gain conversion transistor connected to the first floating diffusion region; a first row booster block connected to the first gain conversion transistor and a second gain conversion transistor that is included in a second unit pixel adjacent to the first unit pixel in the row direction; and a first column booster block connected to the first gain conversion transistor and a third gain conversion transistor that is included in a third unit pixel adjacent to the first unit pixel in the column direction.

A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.