A complementary metal-oxide-semiconductor (CMOS) image sensor with silicon and silicon germanium is provided. A silicon germanium layer abuts a silicon layer. A photodetector is arranged in the silicon germanium layer. A transistor is arranged on the silicon layer with a source/drain region that is buried in a surface of the silicon layer and that is electrically coupled to the photodetector. A method for manufacturing the CMOS image sensor is also provided.

An infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor.

There is provided an image sensor including pixels each configured to include a transfer transistor configured as an embedded channel type MOS transistor and to output a pixel signal based on a charge transferred to a floating diffusion from a photodiode by the transfer transistor in an on state, and a determination unit configured to convert the output pixel signal to a digital value, then compare the converted digital value to a threshold value, and thereby make a binary determination on presence or absence of incidence of a photon on the pixel that has generated the pixel signal.

An image sensor includes at least one pixel with a transfer gate that is controllable among at least three biasing conditions, including a first biasing condition in which electrons are transferable from a photodiode to a potential well under the transfer gate, a second biasing condition in which the electrons are confined in the potential well under the transfer gate, and a third biasing condition in which the electrons are transferable out of the potential well under the transfer gate. The pixel includes a p+ type doped barrier implant located at least partially under a portion of the transfer gate, and a pinned charge transfer barrier located on the opposite side of the transfer gate from the photodiode that includes a p+ type doped region and an n-type doped region. The image sensor can operate in a global shutter mode and/or a rolling shutter mode.

Provided is a complementary metal-oxide-semiconductor (CMOS) image sensor. The CMOS image sensor can include a substrate having a first device isolation layer defining and dividing a first active region and a second active region, a photodiode disposed in the substrate and can be configured to vertically overlap the first device isolation layer, a transfer gate electrode can be disposed in the first active region and can be configured to vertically overlap the photodiode, and a floating diffusion region can be in the first active region. The transfer gate electrode can be buried in the substrate.

Provided is a semiconductor device which can reduce leakage of current between wirings. Included steps are forming a first insulator over a first conductor which is formed over substrate; forming a first hard mask thereover; forming a first resist mask comprising a first opening, over the first hard mask; etching the first hard mask to form a second hard mask comprising a second opening; etching the first insulator using the second hard mask to form a second insulator comprising a third opening; forming a second conductor embedded in the second opening and the third opening; performing polishing treatment on the second hard mask and the second conductor to form a third conductor embedded in the third opening; forming a fourth conductor thereover; forming a second resist mask in a pattern over the fourth conductor; and dry-etching the fourth conductor to form a fifth conductor. The second hard mask can be dry-etched.

In a semiconductor device in which a plurality of light receiving elements are provided in each of a plurality of pixels that form a solid-state image sensor, a decrease in the performance of the semiconductor device is prevented, the decrease occurring due to an increase in the number of wires. In the pixel having a first photodiode and a second photodiode, a first transfer transistor coupled to the first photodiode and a second transfer transistor coupled to the second photodiode are respectively controlled by the same gate electrode, thereby allowing the number of wires for controlling the first and the second transfer transistors is reduced.

A unit pixel formed on a substrate and configured to convert incident light to an electrical signal is provided. The unit pixel includes: a source having a source voltage supplied thereto and having a silicide layer for metal contact formed thereabove; a drain spaced apart from the source and having a silicide layer for metal contact formed thereabove; a channel formed between the source and the drain and having a current flowed therethrough; an insulating layer formed above the channel; and a floating gate having a nonsal structure in which no silicide layer is formed thereabove in order to facilitate an absorption of light, formed above the insulating layer so as to be placed between the source and the drain, and configured to control an amount of current flowing through the channel by an electric field generated by electron-hole pairs generated by the incident light. A body of the unit pixel is floated, and the electric field is configured to act on the channel by electrons aggregated toward the source and holes aggregated toward the drain by the source voltage supplied to the source.

An imaging device according to an embodiment of the present invention includes a plurality of pixels. Each of the pixels has an active region including a first region and a second region with an electrode therebetween in plan view. A portion that is a portion of the active region and that is located under the electrode forms at least a portion of a capacitor. The first region includes a first semiconductor region of a first conductivity type that forms at least a portion of a floating diffusion, and the second region includes a second semiconductor region of a second conductivity type opposite to the first conductivity type. An insulating film is disposed on the second semiconductor region.

A sensor comprises a substrate; an array of nanowire field effect transistors (NWFETs) formed in said substrate, each of the NWFETs having source, drain and gate terminals; a nanowire coupled between the source terminal and the drain terminal of each NWFET; and a layer of radiation sensitive material disposed over said NWFETs and said nanowires with each of the source, drain and gate terminals configured to be coupled to respective ones of first, second or third reference potentials, wherein each NWFET is configured such that the conductivity between the source and drain changes in response to radiation absorbed in the layer of radiation sensitive material such that the sensor generates an output signal in response to radiation absorbed by the radiation sensitive material.