Patent classifications
H10F39/014
DUAL WAVELENGTH IMAGING CELL ARRAY INTEGRATED CIRCUIT
A semiconductor device is provided that includes an array of imaging cells realized from a plurality of layers formed on a substrate, wherein the plurality of layers includes at least one modulation doped quantum well structure spaced from at least one quantum dot structure. Each respective imaging cell includes an imaging region spaced from a corresponding charge storage region. The at least one quantum dot structure of the imaging region generates photocurrent arising from absorption of incident electromagnetic radiation. The at least one modulation doped quantum well structure defines a buried channel for lateral transfer of the photocurrent for charge accumulation in the charge storage region and output therefrom. The at least one modulation doped quantum well structure and the at least one quantum dot structure of each imaging cell can be disposed within a resonant cavity that receives the incident electromagnetic radiation or below a structured metal film having a periodic array of holes.
CMOS IMAGE SENSOR STRUCTURE WITH IR/NIR INTEGRATION
A semiconductor device includes a substrate, light sensing devices, at least one infrared radiation sensing device, a transparent insulating layer, an infrared radiation cut layer, a color filter layer and an infrared radiation color filter layer. The light sensing devices and the at least one infrared radiation sensing device are disposed in the substrate and are adjacent to each other. The transparent insulating layer is disposed on the substrate overlying the light sensing devices and the at least one infrared radiation sensing device. The infrared radiation cut layer is disposed on the transparent insulating layer overlying the light sensing devices for filtering out infrared radiation and/or near infrared radiation. The color filter layer is disposed on the infrared radiation cut layer. The infrared radiation color filter layer is disposed on the transparent insulating layer overlying the at least one infrared radiation sensing device.
DEEP TRENCH ISOLATION FABRICATION FOR BSI IMAGE SENSOR
The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.
Insulating wall and method of manufacturing the same
A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.
Method of manufacturing semiconductor unit and the semiconductor unit
In a solid-state imaging device including a plurality of pixels each pixel including a plurality of photodiodes, it is prevented that an incidence angle of incident light on the solid-state imaging device becomes large in a pixel in an end of the solid-state imaging device, causing a difference in output between the two photodiodes in the pixel, and thus autofocus detection accuracy is deteriorated. Photodiodes extending in a longitudinal direction of a pixel allay section are provided in each pixel. The photodiodes in the pixel are arranged in a direction orthogonal to the longitudinal direction of the pixel allay section.
SOLID-STATE IMAGE PICKUP ELEMENT AND IMAGE PICKUP APPARATUS
A solid-state image pickup element including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type.
IMAGE SENSING DEVICE AND MANUFACTURING METHOD THEREOF
Some embodiments of the present disclosure provide a back side illuminated. (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.
Method of fabricating semiconductor image sensor device having back side illuminated image sensors with embedded color filters
Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.
Buried channel deeply depleted channel transistor
Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
High efficiency wide spectrum sensor
An optical sensor including a first material layer comprising at least a first material; a second material layer comprising at least a second material that is different from the first material, where a material bandgap of the first material is larger than a material bandgap of the second material; and a graded material layer arranged between the first material layer and the second material layer, the graded material layer comprising an alloy of at least the first material and the second material having compositions of the second material that vary along a direction that is from the first material to the second material.