A pixel arrangement is provided. The pixel arrangement includes a photosensitive stage being configured to generate electrical signals by converting electromagnetic radiation, wherein the photosensitive stage forms at least one sub-pixel of a first type including a photodiode that is configured generate a low sensitivity signal, and at least one sub-pixel of a second type including a photodiode that is configured to generate a high sensitivity signal. The pixel arrangement further includes a sample-and-hold stage, wherein the sample-and-hold stage is electrically coupled to the photosensitive stage via a diffusion node and configured to sample and store the electrical signals from the photosensitive stage.

Disclosed is a complementary metal oxide semiconductor (CMOS) image sensor. The image sensor comprises a first separation zone in a substrate, the first separation zone defining first and second pixel regions arranged in a first direction, the first separation zone including first parts substantially parallel extending in the first direction, and the substrate including a first active region vertically overlapping one of the first parts and a second active region vertically overlapping another of the first parts. The image sensor further comprises first and second photoelectric conversion devices arranged in the first direction on at least one of the first and second pixel regions in the substrate, and a source follower gate on the first active region of the substrate.

An image sensor and a method of fabricating the same are disclosed. The image sensor may include a substrate including an active region defined by a device isolation layer, a photoelectric conversion layer, a well impurity layer, a floating diffusion region, and a transfer gate. When viewed in a plan view, a lower portion of the transfer gate may include a first surface in contact with the device isolation layer, a second surface substantially perpendicular to the first surface, and a third surface connected to the first and second surfaces. The third surface may face the floating diffusion region. A first portion of a gate insulating layer may be adjacent to the third surface and thinner than a portion adjacent to the first surface or the second surface, and this may facilitate more efficient transfer of an electron from the photoelectric conversion layer to the floating diffusion region.

A pixel circuit within an integrated-circuit image sensor includes a photodiode having a pinning layer of a first conductivity type, a floating diffusion node and a transfer gate disposed between the photodiode and the floating diffusion node. A first control input is coupled to the transfer gate, and a second control input is coupled to the pinning layer of the photodiode to enable the depletion potential of the photodiode to be raised and lowered.

Provided is a complementary metal-oxide-semiconductor (CMOS) image sensor. The CMOS image sensor can include a substrate having a first device isolation layer defining and dividing a first active region and a second active region, a photodiode disposed in the substrate and can be configured to vertically overlap the first device isolation layer, a transfer gate electrode can be disposed in the first active region and can be configured to vertically overlap the photodiode, and a floating diffusion region can be in the first active region. The transfer gate electrode can be buried in the substrate.

A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.

Methods for forming image sensor structures are provided. The method includes forming an isolation structure in a substrate and forming a first light sensing region and a second light sensing region. The method further includes forming a first gate structure and a second gate structure, and the first gate structure and the second gate structure are positioned at a front side of the substrate. The method further includes forming a first source/drain structure adjacent to the first gate structure and a second source/drain structure adjacent to the second gate structure and forming an interlayer dielectric layer over the front side of the substrate. The method further includes forming a contact trench through the interlayer dielectric layer and forming a contact in the contact trench.

The present technology relates to a solid-state imaging device and an electronic apparatus that realize a high frame rate image capture without deteriorating an image quality. A floating diffusion holds a charge accumulated on one or more photoelectric conversion units. A plurality of amplification transistors read out a signal corresponding to the charge held by the floating diffusion. The signal read out by the amplification transistor is output to a vertical signal line. The plurality of amplification transistors are connected in parallel. The present technology is applicable to a CMOS image sensor, for example.

A complementary metal oxide semiconductor (CMOS) image sensor is provided that includes a substrate including a first surface, a second surface facing the first surface, and a first recess region that is recessed from the first surface toward the second surface. The CMOS image sensor further includes a transfer gate on the substrate, and a source follower gate on the first recess region. The source follower gate is within the first recess region and partially covers a portion of the first surface of the substrate.

A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.