An image sensor includes a photodiode disposed in a substrate and including an n-type impurity region, wherein the n-type impurity region is doped with n-type impurities, a transfer gate (TG) structure partially buried in the substrate and disposed on the n-type impurity region, a recess disposed at an upper surface of the substrate and being spaced apart from the TG structure, a floating diffusion (FD) region disposed under the recess and doped with n-type impurities, and an impurity region disposed at a portion of the substrate between the TG structure and the recess and doped with p-type impurities. An upper surface of the FD region is lower than an upper surface of the impurity region.

An image sensor includes a first substrate. A photoelectric conversion region is in the first substrate. A first interlayer insulating layer is on the first substrate. A transistor includes a bonding insulating layer on the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer. A bias pad is spaced apart from the semiconductor layer by the bonding insulating layer. The bias pad overlaps the first gate in a planar view. A second interlayer insulating layer covers the transistor.

A solid-state imaging device capable of preventing variation in bonding strength in a bonding plane between a first semiconductor substrate and a second semiconductor substrate is provided. The solid-state imaging device includes a first semiconductor substrate having a plurality of first conductors, and a second semiconductor substrate bonded to the first semiconductor substrate and having a plurality of second conductors In a bonding plane between the first and second semiconductor substrates, the device includes regions where the conductors overlap, regions where insulating films and the conductors overlap, and regions where the insulating films overlap. The proportion of areas where the first insulating films and the second insulating films are bonded together to the bonding area between the first semiconductor substrate and the second semiconductor substrate is constant before and after the first semiconductor substrate and the second semiconductor substrate are bonded together.

The present description concerns a pixel array comprising one or a plurality of pixels (PIX1). Each pixel comprises a first transistor having its control node coupled to a photodiode, a first main conduction node coupled to a first output voltage rail (VS), and a second main conduction node coupled to a second voltage rail (VCS). The array comprises a variable impedance (404) coupling the first voltage rail (VS) to a first power supply rail (VDD) and a current source (402) coupling the second voltage rail (VCS) to a second power supply rail (GND), the variable impedance (404) being controlled based on a voltage on the second voltage rail (VCS). The array comprises a first switch (4002) coupling the second voltage rail (VCS) to a third voltage rail (VINIT1).

An image sensor includes a first column line and a second column line configured to extend in a first direction, a plurality of pixel groups configured to connect to the first column line or the second column line and to comprise a plurality of pixels in each of the plurality of pixel groups, a bias circuit configured to comprise a first current circuit and a second current circuit configured to output different bias currents in a first operational mode, and a switching circuit configured to connect the first column line to the first current circuit and connect the second column line to the second current circuit during a first time period, and to connect the first column line to the second current circuit and connect the second column line to the first current circuit during a second time period subsequent to the first time period in the first operational mode.

An imaging device in which noise can be reduced, and an electronic device using this device. The imaging device includes a light receiving element, and a read circuit. A field effect transistor in the read circuit has a semiconductor layer in which a channel is formed, a gate electrode that covers the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode. The semiconductor layer has a main surface, and a first side surface on one end side of the main surface in a gate width direction of the field effect transistor. The gate electrode has a first portion that faces the main surface via the gate insulating film, and a second portion that faces the first side surface via the gate insulating film. A crystal plane of the first side surface is a plane or a plane equivalent to the plane.

It is a main object to provide an image sensor device that can reduce the risks of damage to and/or contamination of its components during manufacturing. The image sensor device according to the present technology is an image sensor device including a substrate and a plurality of sensor units arranged in at least one axis direction on the substrate. Each of the plurality of sensor units includes a pixel chip including a plurality of pixels, and a translucent cover configured to cover the pixel chip. With the image sensor device according to the present technology, there can be provided an image sensor device that can reduce the risks of damage to and/or contamination of its components during manufacturing.

An imaging apparatus includes a semiconductor substrate; a wiring layer located on the semiconductor substrate and including wiring lines; pixel electrodes each located on the wiring layer and having one-to-one correspondence to each of the pixels; a shield electrode located on the wiring layer and disposed between the pixel electrodes; a counter electrode located above the pixel electrodes and the shield electrode; and a photoelectric conversion layer located between the pixel electrodes and the shield electrode and the counter electrode. The wiring layer includes a shield wiring line, and FD wiring lines connected respectively to the pixel electrodes. There is a one-to-one correspondence between each of the FD wiring lines and each of the pixel electrodes. The shield wiring line is connected to the shield electrode. The shield wiring line includes openings each overlapping with at least one of the FD wiring lines in a plan view.

An array substrate, a display panel, and an electronic device are provided. The array substrate includes a substrate, a first conductive layer including a first connection part, a fourth insulating layer disposed on the first conductive layer and provided with a second via, and a second conductive layer disposed on the fourth insulating layer and in the second via. The second conductive layer includes a second electrode, and the second electrode is connected to the first connection part through the second via.

A method of fabricating a unit cell of a focal plane array includes providing an integrated circuit substrate, depositing a proximal portion of a dielectric layer on the substrate, and etching a plurality of recess structures into the dielectric layer. Each of the plurality of recess structures defines a partial via and includes sidewalls that extend from the first surface to a bottom portion of the respective recess structure. The method also includes forming a capacitor structure, depositing a distal portion of the dielectric layer on the capacitor structure and a region of the proximal portion of the dielectric layer, forming a plurality of vias passing to the capacitor structure, forming a metal layer, and forming a detector overlying the metal layer. The plurality of vias are positioned between the capacitor structure and the metal layer and electrically connect the capacitor structure to the metal layer.