The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.

The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect layer disposed on a substrate, where the first electrode bilayer includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the dielectric layer where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.

To provide a thin film capacitor in which warpage is less likely to occur. A thin film capacitor includes: a metal foil having roughened upper and lower surfaces; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a dielectric film covering the lower surface of the metal foil and made of a dielectric material having a thermal expansion coefficient smaller than that of the metal foil; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the first dielectric film without contacting the metal foil. The lower surface of the metal foil is thus covered with the dielectric film having a small thermal expansion coefficient, thereby making it possible to prevent the occurrence of warpage.

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing a semiconductor structure includes: forming a plurality of capacitor holes on a substrate, and exposing a part of the substrate on bottoms of the capacitor holes; forming a bottom electrode layer on surfaces of the capacitor holes; forming, on a surface of the bottom electrode layer, a dielectric layer continuously covering the surface of the bottom electrode layer; forming a first top electrode layer to continuously cover a surface of the dielectric layer by a first film forming process; by a second film forming process, forming, in a circumferential direction of the capacitor holes, a second top electrode layer continuously covering a surface of the first top electrode layer, and forming, in an axial direction of the capacitor holes.

A semiconductor structure includes a capacitor structure and a contact structure. The capacitor structure includes an electrode layer, a protective dielectric layer, and a capacitor dielectric layer. The protective dielectric layer covers a top surface of the electrode layer. The capacitor dielectric layer is on the protective oxide layer. The contact structure penetrates the protective oxide layer and electrically connects to the electrode layer.

The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.

A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer is positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.