A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.

A method of fabricating a semiconductor device, the method including: forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film.

In some embodiments, the present disclosure relates to an integrated chip structure that includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a first electrode and a second electrode stacked over the substrate. A dielectric layer is arranged between the first electrode and the second electrode. A getter layer is disposed over the substrate and is separated from the dielectric layer by the first electrode. The MIM device includes a middle portion having a first non-zero concentration of hydrogen and a peripheral portion having both a second non-zero concentration of hydrogen that is greater than the first non-zero concentration and a third non-zero concentration of hydrogen that is less than the first non-zero concentration. The middle portion includes the dielectric layer and the peripheral portion includes the getter layer.

Provided are a capacitor of a semiconductor integrated circuit and a method for manufacturing the same, for example a metal-insulator-metal (MIM) type capacitor of a semiconductor integrated circuit, which is capable of improving adhesive force between an electrode layer and a dielectric layer of a capacitor, and a method for manufacturing the same. For example, the present disclosure provides a capacitor for a semiconductor integrated circuit having a new structure, which is capable of preventing a delamination phenomenon on an interface between a lower electrode layer and a dielectric layer by further forming a buffer layer, which is capable of decreasing or compensating for a difference in a coefficient of thermal expansion, between a metal electrode layer and a dielectric layer, particularly, between the lower electrode layer and the dielectric layer, and a method for manufacturing the same.

An electronic component includes a body part and a via part. The body part includes first and second metal layers disposed with at least one dielectric layer interposed therebetween. The via part is disposed in the body part and includes first and second vias penetrating through the body part and selectively connected to the first and second metal layers, respectively. The first and second metal layers contain different metals. In some examples, a first insulating film is disposed between the first metal layer and the second via to electrically insulate the second via from the first metal layer, and a second insulating film is disposed between the second metal layer and the first via to electrically insulate the first via from the second metal layer. A method for forming the electronic component includes use of first and second etchants to selectively etch the first and second metal layers.

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

Vertical metal-insulator-metal (MIM) capacitors include a metal conductor including a sidewall; a high k dielectric layer on the sidewall of the metal conductor; and a vertically oriented metal layer on the high k dielectric layer. Also disclosed are methods for fabricating the vertical MIM capacitor, wherein a single patterning/mask process can used to fabricate the vertical MIM capacitor structure.

A semiconductor device includes a substrate, a conductive pattern on the substrate, a lower electrode electrically connected to the conductive pattern, a dielectric layer covering a surface of the lower electrode, a first upper electrode on the dielectric layer, a diffusion barrier on an upper surface of the first upper electrode, and a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode.

Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.