A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

A semiconductor device includes a substrate having fins and trenches in between the fins, a plurality of insulators, a first metal layer, an insulating layer, a second metal layer and an interlayer dielectric. The insulators are disposed within the trenches of the substrate. The first metal layer is disposed on the plurality of insulators and across the fins. The insulating layer is disposed on the first metal layer over the plurality of insulators and across the fins. The second metal layer is disposed on the insulating layer over the plurality of insulators and across the fins. The interlayer dielectric is disposed on the insulators and covering the first metal layer, the insulating layer and the second metal layer.

Embodiments of present invention provide a test structure. The test structure includes a scribe line area in a semiconductor substrate; a first fin and a second fin in the scribe line area and an insulating region between the first fin and the second fin; a first epitaxial region directly on top of the first fin and a second epitaxial region directly on top of the second fin; and an under-test region on top of the insulating region in the scribe line area and between the first epitaxial region and the second epitaxial region. In one aspect, the under-test region includes a gate and a first and a second sidewall spacer formed at a first and a second sidewall of the gate, the first epitaxial region being in contact with the first sidewall spacer and the second epitaxial region being in contact with the second sidewall spacer.

An antifuse-type memory includes a first memory cell. The first memory cell includes a first select transistor, a first following transistor and a first antifuse transistor. A first drain/source terminal of the first select transistor is connected with a first bit line. A gate terminal of the first select transistor is connected with a first word line. A first drain/source terminal of the first following transistor is connected with a second drain/source terminal of the first select transistor. A gate terminal of the first following transistor is connected with a first following control line. The first antifuse transistor includes a first fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. The first gate structure includes a first gate dielectric layer and a first gate layer. The first gate layer is connected with a first antifuse control line.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.

A semiconductor device includes a first and second active regions extending in a first direction and having respective first and second widths in a second direction, the second width greater than the first width, a connection region connected to the first and second active regions and having a third width, between the first and second widths in the second direction, first and second gate structures respectively intersecting the first and second active regions and extending in the second direction, and a dummy structure intersecting at least a portion of the connection region, extending in the second direction, and between the first and second gate structures in the first direction. The dummy structure includes first and second pattern portions spaced apart from a side surface of the first gate structure by respective first and second distances in the first direction, the second distance greater than the first distance.