A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.

According to one embodiment, an inter-electrode insulating film interposed between a floating gate electrode and a control gate electrode includes a lower layer insulating film disposed on a side closer to the floating gate electrode, an upper layer insulating film disposed on a side closer to the control gate electrode, and an intermediate insulating film interposed between the lower layer insulating film and the upper layer insulating film, wherein the intermediate insulating film contains a first element, and the lower layer insulating film contains the first element and a second element, such that a ratio of the first element relative to the second element is larger on a side closer to the intermediate insulating film than on a side closer to the floating gate electrode.

A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

A semiconductor structure includes a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.

Methods for forming a transistor include forming a gate conductor in contact with a gate stack. The gate conductor has a top surface that meets a middle point of sidewalls of a sacrificial region of a fin. The sacrificial region of the fin is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor. The top spacer includes airgaps above the gate stack.

A transistor includes a vertical channel fin directly on a bottom source/drain region. A gate stack is formed on sidewalls of the vertical channel fin. A top spacer is formed over the gate stack. The top spacer has air gaps directly above the gate stack. A top source/drain region is formed directly on a top surface of the vertical channel fin.

A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer of the first region and the second region; forming a stop layer on the first region and the second region; removing the stop layer on the second region; and forming a second BBM layer on the first region and the second region.

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.