A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.

A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200 C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.

A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k dielectric layer, the first high-k dielectric layer having a first thickness and comprising hafnium. The second circuit element comprises a second electrode structure that includes a second high-k dielectric layer having a ferroelectric behavior, wherein the second high-k dielectric layer has a second thickness and comprises hafnium, and wherein the second thickness is greater than the first thickness.

A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Disclosed are a ferroelectric semiconductor thin film, a method of forming the ferroelectric semiconductor thin film, a transistor, a memory device and an integrated circuit. The method of forming the ferroelectric semiconductor thin film includes preparing a precursor solution including an indium precursor and a selenium precursor, and performing spray pyrolysis of the precursor solution on a substrate to obtain the ferroelectric semiconductor thin film including a polycrystalline -In.sub.2Se.sub.3 layer.

Provided is a semiconductor device including a channel layer including a semiconductor material, a ferroelectric layer arranged on the channel layer and including a ferroelectric material, a gate electrode arranged on the ferroelectric layer, a first insertion layer arranged between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer arranged between the channel layer and the ferroelectric layer and including a second paraelectric material having a dielectric constant higher than a dielectric constant of the first paraelectric material.

A non-volatile memory cell includes a capacitor which includes a top electrode, a bottom electrode, a ferroelectric layer disposed between the top electrode and the bottom electrode, and an amorphous layer disposed between the top electrode and the bottom electrode, wherein an atomic arrangement of the amorphous layer is different from an atomic arrangement of the top electrode and the bottom electrode. A method of fabricating a non-volatile memory cell and a memory cell array thereof are also disclosed.

A method of making a semiconductor die includes forming, over a substrate, a stack including insulating layers and sacrificial layers alternatively on top of each other; replacing a portion of first sacrificial layers located in a first portion of the stack to form first gate layers; forming first channel layers extending in a first direction in the first portion; forming first memory layers extending in the first direction in the first portion; replacing a portion of second sacrificial layers located in a second portion of the stack to form second gate layers; forming second channel layers extending in the first direction in the second portion; and forming second memory layers extending in the first direction in the second portion.