The present invention concerns semiconductor devices comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, MoTe.sub.2 or WTe.sub.2. Replacing a stack by only one or two 2-dimensional layer(s) of MoS.sub.2, MoSe.sub.2, WS.sub.2, or WSe.sub.2, MoTe.sub.2 or WTe.sub.2 provides an enhanced electrostatic control, low power dissipation, direct band gap and tunability.

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide.

Provided are a thin film structure, a semiconductor device including the thin film structure, and a semiconductor apparatus including the semiconductor device. The thin film structure includes a substrate, and a ferroelectric layer on the substrate. The ferroelectric layer includes a compound having fluorite structure, in which a <001> crystal direction is aligned in a normal direction of a substrate, and having an orthorhombic phase and including fluorine. The ferroelectric layer may have ferroelectricity.

Disclosed are a 3D non-volatile memory, an operating method thereof, and a manufacturing method thereof. The 3D non-volatile memory includes a bit line formed to extend in a vertical direction and horizontal structures contacting the bit line while being formed to extend in a horizontal direction and being space in the vertical direction. Each of the horizontal structures includes a ferroelectric layer contacting the bit line, a middle metal layer surrounded by the ferroelectric layer, a dielectric layer surrounded by the middle metal layer, and a word line surrounded by the dielectric layer.

Structures including a ferroelectric field-effect transistor and methods of forming a structure including a ferroelectric field-effect transistor. The structure comprises a semiconductor substrate, a semiconductor layer, a dielectric layer arranged between the semiconductor layer and the semiconductor substrate, and first and second wells in the semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. A ferroelectric field-effect transistor comprises a gate structure on the semiconductor layer over the first well and the second well. The gate structure includes a ferroelectric layer comprising a ferroelectric material.

A ferroelectric memory device includes a first conductive region, a second conductive region and a ferroelectric structure. The second conductive region is disposed over the first conductive region. The ferroelectric structure includes a plurality of different ferroelectric materials stacked between the first conductive region and the second conductive region.

A method includes: forming a bottom electrode over a substrate; depositing a first seed layer over the bottom electrode, the first seed layer having an amorphous crystal phase; performing a first surface treatment on the first seed layer, wherein after the first surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; depositing an upper layer over the dielectric layer; and performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.

Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

A semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate, a gate insulation layer disposed on the ferroelectric layer, metal particles disposed in the gate insulation layer, and a gate electrode layer disposed on the gate insulation layer.