A capacitor of a semiconductor device may include a first electrode, a first seed layer over the first electrode, a first hafnium oxide layer over the first seed layer, a second seed layer over the first hafnium oxide layer, a second hafnium oxide layer over the second seed layer, a third seed layer over the second hafnium oxide layer, a second electrode over the third seed layer, and an interface hafnium oxide layer in contact with at least one of the first seed layer and the second seed layer.

An integrated passive device has a device core of a first metal material and defined by a first side and a second side. Conducting polymer layers are disposed on each of the first side and the second side, and a pattern of one or more direct recesses to the device core are defined in the conducting polymer layers. Bonding material layers are on at least selected areas of the device core that are generally coextensive with the pattern of one or more direct recesses in the conducting polymer layers. First conductive structures of a second metal material different from the first metal material extend from the first side and the second side of the device core. Each of the conductive structures are bonded to a respective one of the bonding material layers. An insulating dielectric encapsulates at least the device core and the conducting polymer layers.

Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

A semiconductor device is described, in which a multi-bridge is packaged in a substrate to improve a small form factor. The semiconductor device comprises a substrate including a first surface and a second surface, which face each other, and defining a first cavity passing through the first surface and the second surface, a first redistribution layer structure formed on the first surface of the substrate, a second redistribution layer structure formed on the second surface of the substrate, a connection terminal disposed on the second redistribution layer structure, and a multi-bridge packaged in the first cavity, including a first bridge facing the first surface and electrically connected to the first redistribution layer structure and a second bridge facing the second surface and electrically connected to the second redistribution layer structure.

A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.

A semiconductor device includes: a first electrode; a booster layer over the first electrode; a hafnium-zirconium based layer over the booster layer; and a second electrode over the hafnium-zirconium based layer.

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.