A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a first conductive material and a second conductive material disposed over the semiconductor substrate and the first dielectric layer. The semiconductor device structure further includes a second dielectric layer surrounding the first conductive material and the second conductive material and an insulating structure over the semiconductor substrate. The insulating structure is disposed between the first conductive material and the second conductive material. The insulating structure comprises a material different from the first dielectric layer and the second dielectric layer.

A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi.sub.2, a second silicide region on the first silicide region, the second silicide region including TiSi.sub.x, and a conductive material on the second silicide region.

A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.

A semiconductor structure and a method for forming the same are provided. One form of the method includes: providing a base, where a channel stack and a tear-off structure span the channel stack being formed on the base, and the channel stack including a sacrificial layer and a channel layer; forming a groove in channel stacks on both sides of a gate structure; laterally etching the sacrificial layer exposed from the groove to form a remaining sacrificial layer; forming a source/drain doped region in the channel layer exposed from the remaining sacrificial layer; forming an interlayer dielectric layer on the base; etching the interlayer dielectric layer on one side of the source region to expose a surface of the channel layer corresponding to the source region; etching the interlayer dielectric layer on one side of the drain region to expose the surface of the channel layer corresponding to the drain region; forming a first metal silicide layer on a surface of the channel layer corresponding to the source region; forming a second metal silicide layer on a surface of the channel layer corresponding to the drain region; forming a first conductive plug covering the first metal silicide layer and a second conductive plug covering the second metal silicide layer. In the present disclosure, contact resistance of the first conductive plug, the second conductive plug, and the source/drain doped region is reduced.

Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D.sub.1 at a top surface, a second dimension D.sub.2 at a bottom surface, and a third dimension D.sub.3 at a location between the top surface and the bottom surface, and wherein each of D.sub.1 and D.sub.2 is greater than D.sub.3.

In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.