Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

A semiconductor device includes a first electrode, a first conductive part, a semiconductor part, a second conductive part, a gate electrode and an insulating part. The first conductive part includes at least one of a metal, a metal oxide, or a metal nitride. The at least one of the metal, the metal oxide, or the metal nitride includes at least one selected from the group consisting of Ti, Ta, W, Cr, and Ru. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first conductive part has a Schottky contact with the first semiconductor region. The second conductive part has a Schottky contact with the second semiconductor region. The second conductive part includes at least one selected from the group consisting of Pt, Ni, Ir, Pd, Au, and Co.

A semiconductor device includes a first electrode, a first conductive part, a semiconductor part, a second conductive part, a gate electrode and an insulating part. The first conductive part includes at least one of a metal, a metal oxide, or a metal nitride. The at least one of the metal, the metal oxide, or the metal nitride includes at least one selected from the group consisting of Ti, Ta, W, Cr, and Ru. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first conductive part has a Schottky contact with the first semiconductor region. The second conductive part has a Schottky contact with the second semiconductor region. The second conductive part includes at least one selected from the group consisting of Pt, Ni, Ir, Pd, Au, and Co.

Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. Subsequently, and separate from the formation of the floating gate structures, at least a portion of the remaining nitride tier material is removed to produce control gate recesses, each adjacent a respective charge storage structure. A control gate is formed in each control gate recess, and the control gate is separated from the charge storage structure by a dielectric structure. In some examples, these dielectric structures are also formed separately from the charge storage structures.

In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

Arrays of memory cells including an isolation region between first and second access lines, a first memory cell having a control gate in contact with the first access line and a charge storage node having a curved cross-section having a first end in contact with a first portion of the isolation region on a first side of the isolation region and a second end in contact with a second portion of the isolation region on the isolation region's first side, and a second memory cell having a control gate in contact with the second access line and a charge storage node having a curved cross-section having a first end in contact with the first portion of the isolation region on a second side of the isolation region and a second end in contact with the second portion of the isolation region on the isolation region's first side.

According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. A 2D material layer is formed over the dielectric layer. An adhesion layer is formed over the 2D material layer. Source/drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed over the adhesion layer, wherein the adhesion layer has a material different from a material of the first high-k gate dielectric layer.