A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.

A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

The present disclosure provides a method for manufacturing a semiconductor device. The method includes: forming a first metal structure in a first ILD layer; planarizing the first metal structure and the first ILD layer, wherein the planarizing generates a groove at an interface of the first metal structure and the first ILD layer; forming an ESL on the first metal structure and the first ILD layer; forming a second ILD layer on the ESL; performing a first etch to remove a portion of the second ILD layer to form a first opening; performing a second etch to remove a portion of the ESL through the opening; performing a third etch to remove a portion of the first ILD layer through the first opening to form a second opening in the first ILD layer; and enlarging the second opening to connected with the groove to form a contact hole.

A method for forming an ohmic contact on a semiconductor component, for example a high-power electrical diode, is provided. An example method includes depositing a first metal layer on a top surface of a semiconductor drift layer having an electrical contact point, the first metal layer highly reflective of a laser light. The method further includes depositing a second metal layer on portions of the first metal layer aligned with the electrical contact point, the second metal layer selected to absorb the laser light. The method further includes exposing the first and the second metal layers to the laser light in a laser annealing process, causing the second metal layer to substantially increase in temperature due to the laser light. The increase in temperature of the second metal layer causing the ohmic contact to form between the electrical contact point and the first metal layer.

A method for manufacturing a semiconductor device includes: forming a transistor on a semiconductor substrate, in which the transistor includes a gate structure and a source/drain structure; forming a patterned dielectric layer on the semiconductor substrate, in which the patterned dielectric layer includes an opening extending from a top surface of the patterned dielectric layer to a top surface of the source/drain structure; forming a dielectric contact spacer to cover a sidewall of the opening; and forming a conductive contact in the opening such that the conductive contact is connected to the source/drain structure and is isolated from the gate structure by the dielectric contact spacer and the patterned dielectric layer.

A dielectric film, which contacts a field plate electrode, is formed between the field plate electrode and a gate electrode, and a recess is formed at an upper surface of the dielectric film and between a drain region and the gate electrode.