One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.

A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

A thin film transistor and a fabrication method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a gate electrode (2), a source electrode (5) and a drain electrode (6) disposed in a same layer on a base substrate (1); a gate insulating layer (3) disposed on the gate electrode (2), the source electrode (5) and the drain electrode (6); an active layer (4) disposed on the gate insulating layer (3); a passivation layer (7) disposed on the active layer (4) and the gate insulating layer (3). A first via hole (81) and a second via hole (91) are disposed in the passivation layer (7); a third via hole (82) and a fourth via hole (92) are disposed in the passivation layer (7) and the gate insulating layer (3); a first connection pattern (8) and a second connection pattern (9) are disposed on the passivation layer (7); the first connection pattern (8) is connected with the active layer (4) and the source electrode (5) through the first via hole (81) and the third via hole (82) respectively; the second connection pattern (9) is connected with the active layer (4) and the drain electrode (6) through the second via hole (91) and the fourth via hole (92) respectively. The thin film transistor effectively reduces the influence of the parasitic capacitance between the source electrode and the gate electrode and the parasitic capacitance between the drain electrode and the gate electrode on the thin film transistor.

A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer, forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, forming sidewalls adjacent to sidewalls of the mandrel, depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.

Various embodiments disclose a method for fabricating one or more vertical fin field-effect-transistors. In one embodiment, a structure is formed. The structure comprises a substrate, a source/drain layer, and a plurality of fins formed on the first source/drain layer. The source/drain layer comprises a first semiconductor layer, a sacrificial layer, and a second semiconductor layer. A bottom spacer layer is formed in contact with the second semiconductor layer and the plurality of fins. A gate structure is then formed. A dielectric layer is deposited in contact with at least the gate structure, the bottom spacer layer, and the second semiconductor layer. At least a portion of the dielectric layer and a portion of the second semiconductor are removed. This removal forms a trench exposing a portion of the sacrificial layer. The sacrificial layer is then removed forming a cavity. A contact material is deposited within the trench and the cavity.

A method for manufacturing an array substrate includes: forming a first conductive pattern and a second conductive pattern on a base substrate; forming a via hole on the base substrate formed with the first conductive pattern and the second conductive pattern, and a lateral side of the via hole being half opened; and forming a jumper wire film on the base substrate formed with the via hole.

When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 110.sup.13 atoms/cm.sup.2 or lower.

An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.

A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained SiGe layers are anchored to one another and a compressive strain is maintained in each of the compressively strained SiGe layers.

A semiconductor device includes a substrate, an insulating layer over the substrate, a metal oxide layer over the insulating layer, and an oxide semiconductor layer over the metal oxide layer. The insulating layer includes a first region overlapping the metal oxide layer and a second region not overlapping the metal oxide layer. A hydrogen concentration of the first region is greater than a hydrogen concentration of the second region. A nitrogen concentration of the first region is greater than a nitrogen concentration of the second region.