A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

A method includes providing a substrate, an isolation structure, and a fin extending from the substrate and through the isolation structure. The fin includes a stack of layers having first and second layers that are alternately stacked and have first and second semiconductor materials respectively. A topmost layer of the stack is one of the second layers. The structure further has a sacrificial gate stack engaging a channel region of the fin. The method further includes forming gate spacers and forming sidewall spacers on sidewalls of the fin in a source/drain region of the fin, wherein the sidewall spacers extend above a bottom surface of a topmost one of the first layers. The method further includes etching the fin in the source/drain region, resulting in a source/drain trench; partially recessing the second layers exposed in the source/drain trench, resulting in gaps; and forming dielectric inner spacers inside the gaps.

In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

The present disclosure describes semiconductor devices and methods for forming the same. A semiconductor device includes nanostructures over a substrate and a source/drain region in contact with the nanostructures. The source/drain region is doped with a first-type dopant. The semiconductor device also includes a counter-doped structure in contact with the substrate and the source/drain region. The counter-doped structure is doped with a second-type dopant opposite to the first-type dopant.

There is provided a thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate and including a channel area, a first conductive area connected to one side of the channel area, and a second conductive area connected to the other side of the channel area; a gate insulating layer covering areas other than the first conductive area and the second conductive area in the semiconductor layer; a gate electrode disposed on the gate insulating layer and overlapping the channel area in a plan view; and a first electrode disposed on the gate insulating layer on the one side of the channel area and in contact with a portion of the first conductive area. A first edge of the first electrode facing the gate electrode obliquely intersects a first edge of the gate insulating layer in a plan view.

A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.

A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.

A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.