Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

A biosensor includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a FET device in the semiconductor layer, an isolation layer over the first surface of the semiconductor layer, a dielectric layer over the isolation layer and the first surface of the semiconductor layer, and a pair of first electrodes and a pair of second electrodes over the dielectric layer and separated from each other. The isolation layer has a rectangular opening substantially aligned with the FET device. The rectangular opening has pair of first sides and a pair of second sides. An extending direction of the pair of first sides is perpendicular to an extending direction of the pair of second sides. The pair of first electrodes is disposed over the pair of first sides, and the pair of second electrodes is disposed over the pair of second sides.

A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.

A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500 C. to 1000 C. inclusive, preferably 550 C. to 750 C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.

The present invention relates to atomically-thin channel materials with crystallographically uniform interfaces to atomically-thin commensurate graphene electrodes and/or nanoribbons separated by nanogaps that allow for nanoelectronics based on quantum transport effects and having significantly improved contact resistances.

Integrated chips and methods of forming the same include forming a gate stack around a first semiconductor fin and a second semiconductor fin. The gate stack around the second semiconductor fin is etched away. An extrinsic base is formed around the second semiconductor fin in a region exposed by etching away the gate stack.