A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

Disclosed are a growth structure for a strained channel, and a strained channel using the same and a method of manufacturing a device using the same. The growth structure for a strained channel includes a support substrate, a strain-relaxed buffer (SRB) layer disposed on a support substrate, a base growth layer grown to have one composition on the SRB layer, and a strained channel layer grown to have another composition on the base growth layer. The strained channel layer may include at least one of a tensile-strained channel layer or a compressively strained channel layer.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.

A layout method and a semiconductor device are disclosed. The layout method includes: generating a design layout by placing a cell, wherein the cell includes: a first conductive segment overlapping a source/drain region and disposed immediately adjacent to a first power rail, wherein the first conductive segment has a length substantially equal to a cell length; a second conductive segment; and a third conductive segment between the first and second conductive segments. The layout method further includes: providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments are aligned in a first direction.

A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer

A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

An integrated circuit device includes a first-type active-region semiconductor structure, a second-type active-region semiconductor structure stacked with the first-type active-region semiconductor structure, a front-side power rail in a front-side conductive layer, and a back-side power rail in a back-side conductive layer. The integrated circuit device also includes a source conductive segment intersecting the first-type active-region semiconductor structure at a source region of a transistor, a back-side power node in the back-side conductive layer, and a top-to-bottom via-connector. The source conductive segment is conductively connected to the front-side power rail through a front-side terminal via-connector. The top-to-bottom via-connector is connected between the source conductive segment and the back-side power node.