Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, semiconductor nanosheets vertically stacked upon one another and disposed above the semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, inner spacers laterally covering the gate structure and interposed between the semiconductor nanosheets, and source/drain (S/D) regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions. A bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets. The S/D regions are separated from the gate structure through the inner spacers.

A semiconductor structure includes a first stacked device having a first field-effect transistor containing one or more first nanosheet layers, a second field-effect transistor containing one or more second nanosheet layers; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width. The semiconductor structure further includes a second stacked device adjacent the first stacked device. The second stacked device having a third field-effect transistor containing one or more third nanosheet layers, a fourth field-effect transistor containing one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer.

An integrated circuit structure includes a first vertical stack of horizontal nanowires or a first fin having a first lateral width. A first gate electrode is over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width. A second vertical stack of horizontal nanowires or a second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the second fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width, the third lateral width less than the first lateral width. A second gate electrode is over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced apart from the first gate electrode, and the second gate electrode having a fourth lateral width, the fourth lateral width less than the second lateral width.

An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.

Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.

Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a first and a second fin-shaped active region over a substrate, the first and second fin-shaped active regions extending lengthwise along a first direction, forming a gate structure over channel regions of the first and second fin-shaped active regions, the gate structure extending lengthwise along a second direction substantially perpendicular to the first direction, forming a trench to separate the gate structure into two segments, the trench extending lengthwise along the first direction and being disposed between the first and second fin-shaped active regions, performing an etching process to enlarge an upper portion of the trench, and forming a gate isolation structure in the trench, and, in a cross-sectional view cut through both the first and second fin-shaped active regions and the gate structure, the gate isolation structure is a T-shape structure.

A semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include: a first trench isolation layer, a protective liner formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The protective liner separates the first trench isolation layer from the second trench isolation layer and the first trench isolation layer is more dense than the second trench isolation layer.