A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

A vertically stacked heterostructure device includes: (1) a substrate; and (2) vertically stacked layers disposed over the substrate and including (a) a source electrode including a layer of graphene; (b) a drain electrode; and (c) a semiconducting channel disposed between the source electrode and the drain electrode. During operation of the device, a current is configured to flow between the source electrode and the drain electrode through the semiconducting channel.

An array substrate, a method for manufacturing the same and a liquid crystal display device are provided. A metal oxide semiconductor layer and an etching stop layer are sequentially formed on a gate insulating layer. One patterning process is performed in the etching stop layer to form a source electrode contact region via hole, a drain electrode contact region via hole and an insulation region. A source-drain electrode layer is formed on the etching stop layer. During a process of performing one patterning process in the source-drain electrode layer to form a source-drain electrode pattern, a portion of the metal oxide semiconductor layer corresponding to the insulation region is removed so that the metal oxide semiconductor layer is disconnected at a position corresponding to the insulation region. The insulation region surrounds the source-drain electrode pattern.

A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

This thin film transistor has a gate electrode, a gate insulating film, an oxide semiconductor thin film, an etch stop layer for protecting the oxide semiconductor thin film, a source and drain electrodes, and a passivation film in this order on a substrate. The oxide semiconductor thin film is formed of an oxide configured from In, Ga and Sn as metal elements, and O, and has an amorphous structure, and the etch stop layer and/or the passivation film includes SiNx. The thin film transistor has an extremely high mobility of approximately 40 cm.sup.2/Vs or more.

To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. By covering a side surface of an oxide semiconductor layer in which a channel is formed with an oxide semiconductor layer, diffusion of impurities into the inside from the side surface of the oxide semiconductor layer is prevented. By forming a gate electrode in a damascene process, miniaturization and high density of a transistor are achieved. By providing a protective layer covering a gate electrode over the gate electrode, the reliability of the transistor is increased.

The concentration of impurity elements included in an oxide semiconductor film in the vicinity of a gate insulating film is reduced. Further, crystallinity of the oxide semiconductor film in the vicinity of the gate insulating film is improved. A semiconductor device includes an oxide semiconductor film over a substrate, a source electrode and a drain electrode over the oxide semiconductor film, a gate insulating film which includes an oxide containing silicon and is formed over the oxide semiconductor film, and a gate electrode over the gate insulating film. The oxide semiconductor film includes a region in which the concentration of silicon is lower than or equal to 1.0 at. %, and at least the region includes a crystal portion.

The EL substrate includes semiconductor layers of TFTs, a pixel electrode, and an upper part electrode of a Cs section which are provided on a gate insulating film. The semiconductor layers are covered with a protective film which has openings via which the pixel electrode and the upper part electrode are exposed. The semiconductor layers are an oxide semiconductor layer, and the pixel electrode and the upper part electrode are reduction electrodes of the oxide semiconductor layer.

An enhancement-mode n-type field effect transistor is disclosed to have a metal oxide channel layer, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The metal oxide channel layer has a material selected from SnO.sub.2, ITO, ZnO, SnO.sub.2 and In2O.sub.3. The metal oxide channel layer has a thickness less than a threshold value to exhibit pinch-off behavior in transfer characteristics and has a mobility trend without saturation under positive operational voltage.