The present invention discloses a three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.

The present invention discloses a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D.sup.2-oP). The mask-patterns for different dice in a same 3D.sup.2-oP package are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different dice in a same 3D.sup.2-oP package.

A semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends.

A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

A semiconductor device that can extend the range of adaptable sampling rate when performing analog/digital conversion is provided. The semiconductor device includes a plurality of sample-and-hold circuits storing an analog signal and a plurality of converter circuits having a function of converting the analog signal stored in the sample-and-hold circuit into a digital signal. The sample-and-hold circuit includes a switch and a capacitor that is supplied with an analog signal through the switch. The switch includes an oxide semiconductor in a channel formation region.

A 3D integrated circuit device, including: a first layer including first transistors, overlaid by a second layer including second transistors, overlaid by a third layer including third transistors, where the first layer, the second layer and the third layer are each thinner than 2 microns, where the first layer includes first circuits including at least one of the first transistors, where the second layer includes second circuits including at least one of the second transistors, and where the third layer includes a charge pump circuit and control circuits to control the first circuits and the second circuits

A semiconductor structure includes a substrate and a vertical stack structure over the substrate. The vertical stack structure includes a channel region and a source/drain region on two sides of the channel region. The channel region includes a first stack region, an isolation region, and a second stack region. The structure also includes a first doped source/drain region, a first contact layer located on a surface of the first doped source/drain region, a second doped source/drain region located over the first contact layer, and a second contact layer located on a surface of the second doped source/drain region. The structure also includes a second connection layer electrically connected to the second doped source/drain region through the second contact layer, and a first connection layer electrically connected to the first doped source/drain region through the first contact layer.

A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first transistor, a first insulator over the first transistor, a second transistor over the first insulator, a second insulator over the second transistor, and a capacitor over the second insulator. The first insulator has a barrier property against oxygen and hydrogen. The second transistor includes an oxide semiconductor. The second insulator includes an oxygen-excess region. The capacitor includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. The dielectric includes a third insulator having a barrier property against oxygen and hydrogen. The first insulator and the third insulator are in contact with each other on an outer edge of a region where the second transistor is located so that the second transistor and the second insulator are enclosed by the first insulator and the third insulator.

A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.