This method comprises the following steps: a) providing a first structure successively comprising a first substrate, a first electronic device, and a first dielectric layer; a second structure successively comprising a second substrate, an active layer, a second dielectric layer, and a polycrystalline semiconductor layer, the active layer being designed to form a second electronic device; b) bombarding the polycrystalline semiconductor layer by a beam of species configured to form an amorphous part and to preserve a superficial polycrystalline part; c) bonding the first and second structures; d) removing the second substrate of the second structure; e) introducing dopants into the amorphous part, through the exposed active layer; f) thermally activating the dopants by recrystallization of the amorphous part.

A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

The technique described herein can form a semiconductor device having a favorable characteristic over a flash memory with a 3D structure. Provided is a method of manufacturing a semiconductor device, including: (a) forming a stacked structure having an insulating film and a sacrificial film stacked therein by performing a combination a plurality of times, the combination including: (a-1) forming the insulating film on a substrate; (a-2) forming the sacrificial film on the insulating film; and (a-3) modifying at least one of the insulating film and the sacrificial film to reduce a difference between stresses of the insulating film and the sacrificial film.

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

A method to form a stacked CMOS image sensor includes forming a signal processing layer including a plurality of discrete signal processing circuit, an image sensor layer including a plurality of discrete image sensing units, and an intermediate capacitor layer including a dielectric layer and a plurality of capacitors. Each capacitor includes a first electrode, a V-shaped or U-shaped first electrode material layer electrically connecting to the first electrode, a second electrode material layer on the first electrode material layer having the dielectric layer there-between, and a second electrode electrically connecting to the second electrode material layer. The method further includes bonding the signal processing layer to the intermediate capacitor layer with each second electrode electrically connected to a signal processing circuit, and bonding the image sensor layer to the intermediate capacitor layer with each first electrode electrically connected to an image sensing unit.

Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.

Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.

The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure. Each of the set of fins has respective cut faces located at the fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends on the set of fins of the FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.