A semiconductor device and a method for manufacturing the same. The semiconductor device comprises an n-channel GAA transistor and a p-channel GAA transistor, which are spaced apart. Each of the n-channel GAA transistor and the p-channel GAA transistor comprises a source, a drain, and at least one nanostructure layer located between the source and the drain. The p-channel GAA transistor further comprises a gate stack structure and a gate sidewall. In the p-channel GAA transistor, the at least one nanostructure layer comprises a channel portion that is covered by the gate stack structure and a connecting portion that is covered by the gate sidewall, and germanium content in the channel portion is greater than germanium content in the connecting portion and is greater than germanium content in the at least one nanostructure layer of the n-channel GAA transistor.

A display device that is suitable for increasing in size is achieved. Three or more source lines are provided for each pixel column. Video signals having the same polarity are input to adjacent source lines during one frame period. Dot inversion driving is used to reduce a flicker, crosstalk, or the like.

A substrate with a -gallium oxide film includes a Si single crystal substrate and a -gallium oxide film provided on the Si single crystal substrate. A substrate with a -gallium oxide film includes a gallium nitride single crystal substrate and a -gallium oxide film provided on the gallium nitride single crystal substrate.

An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 510.sup.19 atoms/cm.sup.3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

A semiconductor device includes a 2-D material channel layer, a gate structure, and source/drain electrodes. The gate structure is over a channel region of the 2-D material channel layer. The source/drain electrodes are over source/drain regions of the 2-D material channel layer, respectively. Each of the source/drain electrodes includes a 2-D material electrode and a metal electrode. The 2-D material electrode is below a bottom surface of a corresponding one of the source/drain regions of the 2-D material channel layer. The metal electrode is over a top surface of the corresponding one of the source/drain regions of the 2-D material channel layer.

A semiconductor device includes a fin-type active region that extends in length in a first horizontal direction on a substrate, a horizontal semiconductor layer on the fin-type active region, a seed layer on the fin-type active region and in contact with the horizontal semiconductor layer, a gate line that surrounds the horizontal semiconductor layer and the seed layer, on the fin-type active region, and that extends in length in a second horizontal direction that intersects the first horizontal direction, and a pair of vertical semiconductor layers respectively on first and second sides of the horizontal semiconductor layer in the first horizontal direction, on the fin-type active region, with the horizontal semiconductor layer therebetween, wherein an inner wall of each of the first and second vertical semiconductor layers contacts the horizontal semiconductor layer, and upper or lower surfaces of the vertical semiconductor layers contact the seed layer.

Provided is a base substrate including an orientation layer used for crystal growth of a nitride or oxide of a Group 13 element, in which a front surface on a side used for the crystal growth of the orientation layer is composed of a material having a corundum-type crystal structure having an a-axis length and/or c-axis length larger than that of sapphire, the orientation layer contains a material selected from the group consisting of -Cr.sub.2O.sub.3, -Fe.sub.2O.sub.3, -Ti.sub.2O.sub.3, -V.sub.2O.sub.3, and -Rh.sub.2O.sub.3, or a solid solution containing two or more selected from the group consisting of -Al.sub.2O.sub.3, -Cr.sub.2O.sub.3, -Fe.sub.2O.sub.3, -Ti.sub.2O.sub.3, -V.sub.2O.sub.3, and -Rh.sub.2O.sub.3, and a half width of an X-ray rocking curve of a (104) plane of the corundum-type crystal structure is 500 arcsec. or less.

The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.