A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium. The first element exists in a state of being bonded to oxygen.

A stack including an active layer, a gate dielectric, and a gate electrode is formed in a forward or in a reverse order, over a substrate. The active layer includes a front channel layer, a bulk semiconductor layer, and a back channel layer. The front channel layer is formed by depositing a layer stack that include at least one post-transition metal oxide layer, a zinc oxide layer, and at least one acceptor-type oxide layer. The zinc oxide layer or at least one post transition metal oxide layer contacts the gate dielectric, and the at least one acceptor-type oxide layer is most distal from the gate dielectric. The front channel layer provides enhanced channel conductivity, while the back channel layer provides suppressed channel conductivity.

A display device includes: a display unit including a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines, and a plurality of pixel circuits; and a drive circuit configured to drive the first scan lines, the second scan lines, and the data lines. Each of the pixel circuits includes: a light-emitting element; a drive transistor configured to control a magnitude of an electric current that flows through the light-emitting element, a first compensation transistor having a control terminal connected to an associated one of the first scan lines; and a second compensation transistor having a control terminal connected to an associated one of the second scan lines. The first and second compensation transistors are connected in series and disposed between a control terminal and a conduction terminal of the drive transistor, the conduction terminal leading to the light-emitting element.

A semiconductor device include a substrate having a gate area and a contact area, a buried insulating layer formed over the substrate, a fin-type insulating pattern formed over the buried insulating layer and extending in a first horizontal direction, a lower metal layer covering an upper surface and side surfaces of the fin-type insulating pattern in the contact pattern, a channel layer covering an upper surface and side surfaces of the lower metal layer in the contact area and covering the upper surface and the side surfaces of the fin-type insulating pattern in the gate area, a gate pattern disposed over the channel layer in the gate area and extending in a second direction, and a source/drain contact pattern disposed over the channel layer in the contact area. The lower metal layer includes a Ti-based metal. The channel layer includes an oxide semiconductor material.

A display panel and a display device are provided. The display panel includes a base substrate, and one or more first transistors and one or more second transistors over the base substrate. A first transistor of the one or more first transistors includes a first active layer, and the first active layer contains silicon. A second transistor of the one or more second transistors includes a second active layer, and the second active layer contains an oxide semiconductor material. The display panel also includes a shielding layer. The shielding layer is disposed on a side of the first active layer facing away from the base substrate, and is disposed on a side of the second active layer facing away from the base substrate. Along a projection direction perpendicular to the base substrate, the shielding layer fully covers the second active layer.

A chamber cleaning method in accordance with an exemplary embodiment includes a chamber stabilizing process for transporting a substrate, on which a thin film deposition process has been completed, out of a chamber and processing an inside of the chamber, wherein the chamber stabilizing process includes: a cleaning process for injecting a cleaning gas into the chamber and etching and cleaning byproducts generated by the thin film deposition; and a coating process for injecting a gas including at least one among aluminum (Al), zirconium (Zr) or hafnium (Hf) into the chamber, and generating a protective film on an inner wall of the chamber and at least one surface of components installed inside the chamber.

An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

Thermal stability of a transistor is improved in different ways. An interfacial layer between a source/drain electrode and a semiconductor layer is formed from a material having a higher bond dissociation energy than indium oxide. Alternatively, the interfacial layer is formed from a metal-doped oxide semiconductor material. As another option, a metal layer or a metal oxide layer is formed between the source/drain electrode and the interfacial layer.