A method of image sensor fabrication includes providing a plurality of photodiodes disposed in a semiconductor material and a floating diffusion disposed in the semiconductor material. The method also includes providing peripheral circuitry disposed in the semiconductor material, including a first electrical contact to the semiconductor material, and forming a transfer gate disposed to transfer image charge from the photodiode to the floating diffusion. An isolation layer is deposited on a surface of the semiconductor material, and contact holes are etched in the isolation layer. A first silicide layer disposed on the floating diffusion, a second silicide layer disposed on the transfer gate, and a third silicide layer disposed on the first electrical contact to the semiconductor material are formed in the contact holes by depositing a silicon layer in the contact holes and metalizing the silicon layer.

An optical receiver module includes a substrate, photodetectors mounted on a first surface of the substrate, amplifiers mounted on the first surface of the substrate, anode wiring patterns formed on the first surface of the substrate and configured to connect between anode terminals of the photodetectors and respective ones of the amplifiers, cathode wiring patterns formed on the first surface of the substrate and configured to connect between cathode terminals of the photodetectors and the respective ones of the amplifiers, a second electrode formed on a second surface of the substrate to cover areas directly opposite, across the substrate, the cathode wiring patterns formed on the first surface, and first vias formed through the substrate in a vicinity of connection points between the cathode wiring patterns and the amplifiers and configured to connect between the cathode wiring patterns and the second electrode.

An image sensing device includes an interconnect layer and a number of grid array contacts arranged on a bottom side of the interconnect layer. An image sensor integrated circuit (IC) is carried by the interconnect layer and has an image sensing surface. A number of electrical connections are coupled between the image sensor IC and an upper side of the interconnect layer. A transparent plate overlies the image sensing surface of the image sensor IC. A cap is carried by the interconnect layer and has an opening overlying transparent plate and the image sensing surface. The cap has an upper wall spaced above the interconnect layer and the image sensor IC to define an internal cavity and the cap defines an air vent coupled to the internal cavity.

A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier.

A method of manufacturing a CMOS image sensor includes providing a semiconductor substrate having a front side and a back side, forming at least two pixels in the front side, forming a shallow trench isolation in the front side between the at least two pixels, forming a deep trench in the back side at a location above the shallow trench isolation, and depositing a dielectric layer in the deep trench to form a crosstalk reduction element.

A stacked semiconductor device structure includes a first semiconductor device having a first major surface and a second major surface opposite to the first major surface. The second major surface includes a recessed region bounded by sidewall portions, and the sidewall portions have outer surfaces defining peripheral edge segments of the first semiconductor device. A first conductive layer is disposed adjoining at least portions of the recessed region. A second semiconductor device having a third major surface and a fourth major surface opposite to the third major surface includes a first portion that is electrically connected to the first conductive layer within the recessed region, and at least a portion of the second semiconductor device is disposed within the recessed region.

A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.

The present disclosure relates to a semiconductor image sensor device. In some embodiments, the semiconductor image sensor device includes a semiconductor substrate having a first surface configured to receive incident radiation. A plurality of sensor elements are arranged within the semiconductor substrate. A first charged layer is arranged on an entirety of a second surface of the semiconductor substrate facing an opposite direction as the first surface. The second surface is between the first charged layer and the first surface of the semiconductor substrate.