A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

The present disclosure provides a method of manufacturing semiconductor chips. The method includes performing a first dry etching process to remove a top metalization layer such that a portion of an interconnect structure is exposed by a scribe line opening after the top metalization layer is removed, wherein the interconnect structure is embedded in a dielectric layer. Next, a first wet etching process using a first etchant is performed to remove a filling layer of the interconnect structure. After performing the first wet etching process, a second wet etching process using a second etchant is performed to remove a glue layer of the interconnect structure. After performing a second wet etching process, a back side stealth dicing process is performed to induce cracks in a substrate from a back side to a front side so as to separate a semiconductor wafer into the semiconductor chips.

A number of semiconductor die with Group III nitride-based amplifier circuits are described. In one example, the semiconductor die includes a first Group III nitride-based transistor having a first output contact. The semiconductor die includes a second Group III nitride-based transistor having a second output contact. The semiconductor die includes an output combiner inductor on the semiconductor die. The output combiner inductor may be coupled to the first output contact and to the second output contact. The output combiner inductor may further be coupled to a radio frequency (RF) output interface for the semiconductor die.

A silicon photonic chip, a LiDAR, and a mobile device are disclosed. The silicon photonic chip includes a cladding, a transceiving waveguide module, a first photoelectric detection module, and a first polarization rotator. An emitting waveguide of the transceiving waveguide module extends along a first direction and is configured to transmit and emit a detection light, and the first receiving waveguide of the transceiving waveguide module is arranged at intervals along a second direction from the emitting waveguide and is configured to receive and transmit an echo light. The first photoelectric detection module is configured to receive a first local oscillator light and the echo light output by the first receiving waveguide. The first polarization rotator is disposed upstream of the first photoelectric detection module.

The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other.

The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions.

A semiconductor device includes a substrate having a fin element extending therefrom. In some embodiments, a gate structure is formed over the fin element, where the gate structure includes a dielectric layer on the fin element, a metal capping layer disposed over the dielectric layer, and a metal electrode formed over the metal capping layer. In some cases, first sidewall spacers are formed on opposing sidewalls of the metal capping layer and the metal electrode. In various embodiments, the dielectric layer extends laterally underneath the first sidewall spacers to form a dielectric footing region.

A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.

An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.