Patent classifications
H10D86/0221
DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE
A display device includes a plurality of pixels arranged in a matrix. Each of the plurality of pixels includes a transistor and a pixel electrode arranged above the transistor through a first protective film and a second protective film. Among the plurality of pixels, the pixel electrodes of two pixels adjacent in a column direction are connected to corresponding source electrodes of the two pixels through second and third contact holes respectively. The second and third contact holes are formed in the first protective film within a first contact hole that is formed in the second protective film.
Array substrate and manufacturing method thereof
An array substrate and a manufacturing method thereof are provided. The array substrate includes a substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer. The array substrate includes a thin film transistor (TFT) area, and the second metal layer includes a source-drain metal sub-layer located in the TFT area. The TFT area is defined with an active layer exposed area. The array substrate includes a barrier layer, and an orthographic projection of the barrier layer on the active layer at least partially covers an orthographic projection of the active layer exposed area on the active layer.
Apparatus and method for a multilayer pixel structure
The present disclosure provides a pixel structure comprising a plurality of layers for providing a touch sensitive pixel of a sensing array. The layers comprising: a thin film transistor; and a conductive layer deposited on a dielectric shield to be touched by an object to be sensed and arranged to provide a capacitive sensing electrode coupled to the thin film transistor. The present disclosure also provides methods of manufacturing such a pixel structure.
Preparation method of oxide thin-film transistor
A preparation method of an oxide thin-film transistor is disclosed, and this method includes: forming a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode; forming of the active layer, the source electrode and the drain electrode includes: sequentially forming an oxide semiconductor thin film and a source-drain electrode metal thin film on a base substrate, an entire surface of the oxide semiconductor thin film being in direct contact with the source-drain electrode metal thin film; and patterning the oxide semiconductor thin film and the source-drain electrode metal thin film with a dual-tone mask so as to form the active layer, the source electrode and the drain electrode by a single patterning process.
MANUFACTURING METHOD OF DUAL GATE OXIDE SEMICONDUCTOR TFT SUBSTRATE AND SUBSTRATE THEREOF
A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.
LEAKAGE-FREE IMPLANTATION-FREE ETSOI TRANSISTORS
A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.
Novel silicon-based backplane structures and methods for display applications
Displays can be fabricated using driver transistors formed with high quality semiconductor channel materials, and switching transistors formed with low quality semiconductor channel materials. The driver transistors can require high forward current to drive emission of the OLED pixels, but might not require very low leakage current. The switching transistors can require low leakage current to allow the pixel capacitor to retain the signal level for accurate OLED device emission, preventing abnormal displays or cross talks.
Display substrate and method for fabricating the same and display device
A display substrate, a method for fabricating the same, and a display device are disclosed. The display substrate comprises a plurality of pixels; and a plurality of slit patterns, which are arranged between at least two of the plurality of pixels, and comprise a plurality of slits arranged in a rubbing direction. Slit patterns are provided, and each of slit patterns comprises slits in the rubbing direction. Thus, during a rubbing alignment process, the slit patterns can guide a rubbing cloth to move in the rubbing direction. Accordingly, the alignment of the rubbing cloth is prevented from changing in the rubbing process, a good alignment layer is formed, rubbing Mura is avoided, and the lifetime of the rubbing cloth is extended.
Structure of dual gate oxide semiconductor TFT substrate
A dual gate oxide semiconductor thin-film transistor (TFT) substrate includes a substrate; a bottom gate positioned on the substrate; a bottom gate isolation layer positioned on the substrate and the bottom gate; a first oxide semiconductor layer positioned on the bottom gate isolation layer above the bottom gate; an oxide conductor layer positioned on the bottom gate isolation layer at one side of the first oxide semiconductor layer; a top gate isolation layer positioned on the first oxide semiconductor layer, the oxide conductor layer, and the bottom gate isolation layer; a top gate positioned on the top gate isolation layer above a middle part of the first oxide semiconductor layer; a source and a drain positioned on the top gate isolation layer at two sides of the top gate; and a passivation layer positioned on the top gate isolation layer, the source, the drain, and the top gate.
Pixel structure of liquid crystal display panel and manufacturing method thereof
A pixel structure of a liquid crystal display panel includes a substrate, a switch device, a pixel electrode, an insulating layer, and a patterned common electrode. The switch device and the pixel electrode are disposed on the substrate, and the switch device is electrically connected to the pixel electrode. The insulating layer is disposed on the substrate and covers the switch device and the pixel electrode, wherein the insulating layer includes a plurality of trenches. The patterned common electrode is disposed on the insulating layer and does not cover the trenches. The pixel structure of the liquid crystal display panel and related manufacturing method are able to enhance the driving effect of the liquid crystal molecules, reduce the driving voltage and increase alignment performance of the alignment film.