Structure of dual gate oxide semiconductor TFT substrate

Abstract

A dual gate oxide semiconductor thin-film transistor (TFT) substrate includes a substrate; a bottom gate positioned on the substrate; a bottom gate isolation layer positioned on the substrate and the bottom gate; a first oxide semiconductor layer positioned on the bottom gate isolation layer above the bottom gate; an oxide conductor layer positioned on the bottom gate isolation layer at one side of the first oxide semiconductor layer; a top gate isolation layer positioned on the first oxide semiconductor layer, the oxide conductor layer, and the bottom gate isolation layer; a top gate positioned on the top gate isolation layer above a middle part of the first oxide semiconductor layer; a source and a drain positioned on the top gate isolation layer at two sides of the top gate; and a passivation layer positioned on the top gate isolation layer, the source, the drain, and the top gate.

Claims

1. A structure of a dual gate oxide semiconductor thin-film transistor (TFT) substrate, comprising a substrate; a bottom gate positioned on the substrate; a bottom gate isolation layer positioned on the substrate and the bottom gate; a first oxide semiconductor layer positioned on the bottom gate isolation layer above the bottom gate; an oxide conductor layer positioned on the bottom gate isolation layer at one side of the first oxide semiconductor layer; a top gate isolation layer positioned on the first oxide semiconductor layer, the oxide conductor layer, and the bottom gate isolation layer; a top gate positioned on the top gate isolation layer above a middle part of the first oxide semiconductor layer; a source and a drain positioned on the top gate isolation layer at two sides of the top gate; and a passivation layer positioned on the top gate isolation layer, the source, the drain, and the top gate; wherein two areas of the first oxide semiconductor layer are ion doping conductor layers; the top gate isolation layer is provided with first via holes correspondingly above the two side areas of the first oxide semiconductor layer; the top gate isolation layer is provided with a second via hole correspondingly above the oxide conductor layer; and the top gate isolation layer and the passivation layer are provided with a third via hole correspondingly above the oxide conductor layer; wherein the source and the drain respectively contact with the two side areas of the first oxide semiconductor layer through the first via holes; the source contacts with the oxide conductor layer through the second via hole; and the third via hole exposes a portion of the oxide conductor layer; wherein the bottom gate, the first oxide semiconductor layer, the source, the drain and the top gate construct a dual gate TFT; and the oxide conductor layer constructs a pixel electrode of a liquid crystal display (LCD); wherein a material of the first oxide semiconductor layer is indium gallium zinc oxide (IGZO), and the oxide conductor layer is manufactured by implementing ion doping to the IGZO semiconductor layer; and wherein materials of the bottom gate isolation layer and the top gate isolation layer are silicon nitride, silicon oxide, or a combination of the two.

2. The structure of the dual gate oxide semiconductor TFT substrate according to claim 1, wherein materials of the bottom gate, the top gate, the source and the drain are a stack combination of one or more of molybdenum, titanium, aluminum, and copper.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to better understand the characteristics and technical aspect of the invention, please refer to the following detailed description of the present invention is concerned with the diagrams, however, provide reference to the accompanying drawings and description only and is not intended to be limiting of the invention.

(2) In the drawing:

(3) FIG. 1 is a sectional diagram of a structure of a dual gate oxide semiconductor TFT substrate applicable for the LCD according to prior art;

(4) FIG. 2 is a flowchart of a manufacture method of a dual gate oxide semiconductor TFT substrate according to the present invention;

(5) FIG. 3 is a diagram of step 1 of the manufacture method of the dual gate oxide semiconductor TFT substrate according to the present invention;

(6) FIG. 4 is a diagram of step 2 of the manufacture method of the dual gate oxide semiconductor TFT substrate according to the present invention;

(7) FIG. 5 is a diagram of step 3 of the manufacture method of the dual gate oxide semiconductor TFT substrate according to the present invention;

(8) FIG. 6 is a diagram of step 4 of the manufacture method of the dual gate oxide semiconductor TFT substrate according to the present invention;

(9) FIG. 7 is a diagram of step 5 of the manufacture method of the dual gate oxide semiconductor TFT substrate according to the present invention;

(10) FIG. 8 is a diagram of step 6 of the manufacture method of the dual gate oxide semiconductor TFT substrate according to the present invention; and

(11) FIG. 9 is a diagram of step 7 of the manufacture method of the dual gate oxide semiconductor TFT substrate according to the present invention and a sectional diagram of a structure of a dual gate oxide semiconductor TFT substrate according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(12) For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings and the specific embodiments.

(13) Referring to FIG. 2, the present invention first provides a manufacture method of a dual gate oxide semiconductor TFT substrate applicable for the LCD, comprising the following steps:

(14) Step 1, referring to FIG. 3, providing a substrate 1, and deposing a first metal layer on the substrate 1, and implementing pattern process to the first metal layer with a first photo process to form a bottom gate 2.

(15) Specifically, the substrate 1 is a transparent substrate. Preferably, the substrate 1 is a glass substrate.

(16) A material of the first metal layer is a stack combination of one or more of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al) and copper (Cu). That is to say, a material of the bottom gate 2 is a stack combination of one or more of molybdenum, titanium, aluminum and copper.

(17) Step 2, referring to FIG. 4, deposing a bottom gate isolation layer 31 on the bottom gate 2 and the substrate 1.

(18) Specifically, material of the gate isolation layer 31 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two.

(19) Step 3, referring to FIG. 5, deposing a transparent oxide semiconductor layer on the bottom gate isolation layer 31, and coating a photoresist layer on the oxide semiconductor layer, and employing a halftone mask to implement a second photo process: first, implementing exposure, development to the photoresist layer to obtain a first photoresist layer 41 covering the oxide semiconductor layer above the bottom gate 2 and a second photoresist layer 42 covering the oxide semiconductor layer at one side of the bottom gate 2; a thickness of two side areas of the first photoresist layer 41 and a thickness of the second photoresist layer 42 are smaller than a thickness of a middle area of the first photoresist layer 41.

(20) Then, the first photoresist layer 41 and the second photoresist layer 42 are employed to implement etching the oxide semiconductor layer for patterning the oxide semiconductor layer to respectively obtain a first oxide semiconductor layer 51 above the bottom gate 2 and a second oxide semiconductor layer 52 at one side of the first oxide semiconductor layer 51.

(21) Specifically, step 3 utilizes physical vapor deposition (PVD) for deposing the transparent oxide semiconductor layer.

(22) A material of the oxide semiconductor layer is indium gallium zinc oxide (IGZO).

(23) Step 4, referring to FIG. 6, first, removing the two side areas of the first photoresist layer 41 and the second photoresist layer 42; employing the remaining middle area of the first photoresist layer 41 as being a mask layer to implement ion doping to the two side areas of the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52, to transform the two side areas of the first oxide semiconductor layer 51 to be a conductor, and to transform the second oxide semiconductor layer 52 to be an oxide conductor layer 52; then, removing the remaining middle area of the first photoresist layer 41.

(24) Step 5, referring to FIG. 7, deposing a top gate isolation layer 32 on the first oxide semiconductor layer 51, the oxide conductor layer 52 and the bottom gate isolation layer 31, and implementing pattern process to the top gate isolation layer 32 with a third photo process, to respectively form first via holes 91 above the two side areas of the first oxide semiconductor layer 51 and a second via hole 92 above the oxide conductor layer 52.

(25) Specifically, step 5 utilizes dry etching for implementing pattern process to the top gate isolation layer 32.

(26) A material of the top gate isolation layer 32 is silicon nitride, silicon oxide, or a combination of the two.

(27) Step 6, referring to FIG. 8, deposing second and third metal layers on the top gate isolation layer 32, and implementing pattern process to the second and third metal layers with a fourth photo process, to respectively obtain a top gate 71 above the first oxide semiconductor layer 51 and a source 81 and a drain 82 at two sides of the top gate 71.

(28) The source 81 and the drain 82 respectively contact with the two side areas of the first oxide semiconductor layer 51 through the first via holes 91; the source 81 contacts with the oxide conductor layer 52 through the second via hole 92.

(29) Specifically, a material of the second and third metal layers is a stack combination of one or more of one or more of molybdenum, titanium, aluminum and copper. That is to say, a material of the source 81, the drain 82 and the top gate 71 is a stack combination of one or more of molybdenum, titanium, aluminum and copper.

(30) Step 7, referring to FIG. 9, deposing a passivation layer 8 on the top gate 71, the source 81, the drain 82 and the top gate isolation layer 32; implementing pattern process to the passivation layer 8 and the top gate isolation layer 32 at the same time with a fifth photo process to obtain a third via 93 above the oxide conductor layer 52.

(31) The bottom gate 2, the first oxide semiconductor layer 51, the source 81, the drain 82 and the top gate 71 construct a dual gate TFT T; the oxide conductor layer 52 constructs a pixel electrode of a LCD.

(32) The aforesaid manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer 52 with ion doping process; the method manufactures the source 81, the drain 82 and the top gate 71 at the same time with one photo process; the method implements patterning process to the passivation layer 8 and the top gate isolation layer 32 together with one photo process, to reduce the number of the photo processes five for shortening the manufacture procedure, raising the production efficiency and lowering the production cost.

(33) Referring to FIG. 9, the present invention further provides a structure of a dual gate oxide semiconductor TFT substrate, comprising a substrate 1, a bottom gate 2 positioned on the substrate 1, a bottom gate isolation layer 31 positioned on the substrate 1 and the bottom gate 2, a first oxide semiconductor layer 51 positioned on the bottom gate isolation layer 31 above the bottom gate 2, an oxide conductor layer 52 positioned on the bottom gate isolation layer 31 at one side of the first oxide semiconductor layer 51, a top gate isolation layer 32 positioned on the first oxide semiconductor layer 51, the oxide conductor layer 52 and the bottom gate isolation layer 31, a top gate 71 positioned on the top gate isolation layer 32 above a middle part of the first oxide semiconductor layer 51, a source 81 and a drain 82 positioned on the top gate isolation layer 32 at two sides of the top gate 71 and a passivation layer 8 positioned on the top gate isolation layer 32, the source 81, the drain 82 and the top gate 71.

(34) Two areas of the first oxide semiconductor layer 51 are ion doping conductor layers; the top gate isolation layer 32 is provided with first via holes 91 correspondingly above the two side areas of the first oxide semiconductor layer 51, and the top gate isolation layer 32 is provided with a second via hole 92 correspondingly above the oxide conductor layer 52, and the top gate isolation layer 32 and the passivation layer 8 are provided with a third via hole 93 correspondingly above the oxide conductor layer 52.

(35) The source 81 and the drain 82 respectively contact with the two side areas of the first oxide semiconductor layer 51 through the first via holes 91; the first source 81 contacts with the oxide conductor layer 52 through the second via hole 92; the third via hole 93 exposes a portion of the oxide conductor layer 52.

(36) The bottom gate 21, the first oxide semiconductor layer 51, the source 81, the drain 82 and the top gate 71 construct a dual gate TFT T; the oxide conductor layer 52 constructs a pixel electrode of a LCD.

(37) Specifically, a material of the first oxide semiconductor layer 51 is IGZO, and the oxide conductor layer 52 is manufactured by implementing ion doping to the IGZO semiconductor layer; material of the bottom gate isolation layer 31 and the top gate layer 32 is silicon nitride, silicon oxide, or a combination of the two; a material of the bottom gate 2, the top gate 71, the source 81 and the drain 82 is a stack combination of one or more of molybdenum, titanium, aluminum and copper.

(38) The aforesaid structure of the dual gate oxide semiconductor TFT substrate positions the oxide conductor layer 52 to be the pixel electrode of the LCD, and the oxide conductor layer 52 and the first oxide semiconductor layer 51 are manufactured by one photo process; the method positions all of the source 81, the drain 82 and the top gate 71 on the top gate isolation layer 32 to simplify the structure of the TFT substrate on one hand and to reduce the number of the photo processes for shortening the manufacture procedure, raising the production efficiency and lowering the production cost on the other hand.

(39) In conclusion, the manufacture method of the dual gate oxide semiconductor TFT substrate provided by the present invention utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer with ion doping process, and the oxide conductor layer is employed as being the pixel electrode of the LCD to replace the ITO pixel electrode in prior art; the method manufactures the source, the drain and the top gate at the same time with one photo process; the method implements patterning process to the passivation layer and the top gate isolation layer together with one photo process, to reduce the number of the photo processes to five for shortening the manufacture procedure, raising the production efficiency and lowering the production cost. The structure of the dual gate oxide semiconductor TFT substrate of the present invention, by positioning the oxide conductor layer to be the pixel electrode of the LCD, and positioning all of the source, the drain and the top gate on the top gate isolation layer, simplifies the structure of the TFT substrate on one hand and reduce the number of the photo processes for shortening the manufacture procedure, raising the production efficiency and lowering the production cost on the other hand.

(40) The above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.