A display device according to an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate; a first insulating layer on the first conductive layer; an active pattern on the first insulating layer and including a semiconductor material; a second insulating layer on the active pattern; and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, a breadth of the first opening is different than a breadth of the second opening, and a side surface of the first opening and a side surface of the second opening are formed to a top surface of the first conductive layer.

A display device includes: a first substrate; a second substrate on the first substrate and exposing a first edge portion of the first substrate, the second substrate protruding beyond a second edge portion of the first substrate; a connection line on the first edge portion of the first substrate, the connection line having a first end portion protruding beyond a first side of the second substrate and a second end portion covered by the second substrate; and a thin-film transistor layer on the second substrate and connected to the connection line. The thin-film transistor layer includes signal lines extending from the first side to a second side of the second substrate. The signal lines extend into contact openings in the thin-film transistor layer and are exposed at a lower part of the second substrate on the second side of the second substrate.

Provided is a display module including a glass substrate, a thin film transistor (TFT) layer provided on a front surface of the glass substrate, a driving circuit provided on a rear surface of the glass substrate and configured to drive the TFT layer, a plurality of light emitting diodes (LED) electrically connected to the TFT layer, a plurality of first connection pads provided at intervals in a portion of the front surface of the glass substrate and electrically connected to a TFT circuit provided in in the TFT layer, a plurality of second connection pads provided at intervals in a portion of the rear surface of the glass substrate and electrically connected to the driving circuit, and a plurality of side wirings extending from the lateral surface of the glass substrate to a portion of an insulating layer and extending to another portion of the insulating layer.

A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about 0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.

A semiconductor device with multiple zero differential transconductance includes: a conductive substrate; a first insulating layer and a second insulating layer disposed on the conductive substrate; a first semiconductor and a second semiconductor disposed on first portions of the first insulating layer and the second insulating layer, respectively; a first buffer layer and a second buffer layer disposed on electrode contact areas of the first semiconductor and the second semiconductor, respectively; and an anode electrode and a cathode electrode disposed on second portions, which are different from the first portions, of the first insulating layer and the second insulating layer and on the first buffer layer and the second buffer layer, respectively, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode.

A display device and a manufacturing method thereof are provided. The display device includes a display area and a non-display area. The display device includes a substrate, an element layer, an electrode pattern layer, a photoresist pattern layer, and a light-emitting element. The element layer is disposed on the substrate. The electrode pattern layer is disposed on the element layer, and the electrode pattern layer includes multiple electrodes. The photoresist pattern layer is disposed on the electrode pattern layer, and the photoresist pattern layer includes a first photoresist pattern disposed corresponding to the display area and corresponding to the electrodes; a second photoresist pattern disposed corresponding to the non-display area and between the electrodes. The light-emitting element is disposed on the photoresist pattern layer and is electrically connected to the electrodes of the electrode pattern layer.

An array substrate and a manufacturing method thereof are provided. The array substrate includes a substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer. The array substrate includes a thin film transistor (TFT) area, and the second metal layer includes a source-drain metal sub-layer located in the TFT area. The TFT area is defined with an active layer exposed area. The array substrate includes a barrier layer, and an orthographic projection of the barrier layer on the active layer at least partially covers an orthographic projection of the active layer exposed area on the active layer.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.