Vertically superimposed lateral gate-all-around metal-oxide-semiconductor field-effect transistors are provided, a structure of a novel three-dimensional integrated circuit such as a CMOS logic circuit that is composed of the vertically superimposed lateral gate-all-around transistors, a random-access memory and the like, and a manufacturing method for the novel three-dimensional integrated circuit are provided. The manufacturing method for the vertically superimposed lateral gate-all-around transistors includes: first preparing a monolayer channel and a source/drain, then protected with a sacrificial layer; preparing an insulating isolation layer, preparing above repeated structures on the insulating isolation layer; preparing an insulating spacer layer between the source/drain and a gate of each of the layers, a gate oxide, a gate, and a source/drain electrode in a unified manner, and finally preparing a connecting wire connected to the outside. The novel three-dimensional integrated circuit can be implemented by connecting the lateral gate-all-around transistors by means of a wire.

The present invention relates to a high-mobility driving element and a method for manufacturing same, the high-mobility driving element comprising: a substrate; an insulating film disposed on the substrate; a channel layer disposed on at least a partial region of the insulating film and including a metal oxide; a source electrode and a drain electrode connected to the channel layer and disposed on the insulating film and either side of the channel layer to face each other; and a protective layer covering all of the channel layer, the source electrode, and the drain electrode, wherein the channel layer comprises a plurality of fluorinated regions in at least a partial region between the source electrode and the drain electrode.

A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

A semiconductor device is provided including frontside interconnects (i.e., metal wires) used mainly as power supplies and backside interconnects (i.e., metal wires) used mainly as signal wiring. The semiconductor device includes a frontside back-end-of-the-line (BEOL) structure including frontside metal wires located in the frontside of the device, and a backside BEOL interconnect structure including backside metal wires located in a backside of the device. At least 90% of the frontside metal wires are power distribution metal wires and at least 90% of the backside metal wires are signal wires.

A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Provided is a metal-oxide thin-film transistor. The metal-oxide thin-film transistor includes a gate, a gate insulation layer, a metal-oxide semiconductor layer, a source electrode, a drain electrode, and a passivation layer that are successively disposed on a base substrate; wherein the source electrode and the drain electrode are both in a laminated structure, wherein the laminated structure of the source electrode or the drain electrode at least includes a bulk metal layer and an electrode protection layer; wherein the electrode protection layer includes a metal or a metal alloy; the electrode protection layer is at least disposed between the metal-oxide semiconductor layer and the bulk metal layer; wherein a metal-oxide layer is disposed between the electrode protection layer and the bulk metal layer.

A thin film transistor, an array substrate and a display device are provided. The thin film transistor is on a base substrate and includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing. The first electrode includes a first overlapping end, an orthographic projection of the first overlapping end on the base substrate at least partially overlaps with an orthographic projection of the first body portion on the base substrate; a first compensation end at a side of the first overlapping end away from the first body portion, an orthographic projection of the first compensation end on the base substrate at least partially overlaps with an orthographic projection of the first extension portion on the base substrate; and a first intermediate portion connecting the first overlapping end and the first compensation end, an orthographic projection of the first intermediate portion on the base substrate is within an orthographic projection of the first spacing on the base substrate.

An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.

Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.

Method to form low-contact-resistance contacts to source/drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.