A semiconductor device includes a first substrate having a first surface and a second opposite surface, a first lower interlayer insulating layer on the second surface, a first active pattern including a first lower pattern contacting the first surface, a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction, a first gate structure on the first lower pattern, a first source/drain pattern on a side of the first gate structure, a second lower interlayer insulating layer including a third surface and a fourth opposite surface, a second active pattern including a second lower pattern contacting the third surface, a plurality of second sheet patterns spaced apart from the second lower pattern in the second direction, a second gate structure on the second lower pattern, wherein the first lower pattern has a first height, and the second lower pattern has a second different height.

A semiconductor device includes gate structures on an insulation structure, the gate structures disposed in a second direction substantially parallel to an upper surface of the insulation structure, source/drain layers at opposite sides, respectively, of each gate structure in a first direction intersecting the second direction, semiconductor patterns disposed in a third direction substantially perpendicular to the upper surface of the insulation structure, the semiconductor patterns extending through each of the gate structures and contacting the source/drain layers, a first division pattern between the gate structures, and a connection pattern extending into and contacting an upper portion of the first division pattern and upper portions of the gate structures adjacent to the first division pattern, a lower surface of the connection pattern being lower than upper surfaces of the gate structures and an upper surface of the connection pattern being higher than the upper surfaces of the gate structures.

An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

An exemplary method of forming a semiconductor device includes forming, in a substrate, an active region protruding vertically from a major surface of the substrate, the active region including a semiconductor source-drain (S/D) region and a first 3-D channel structure, the S/D region physically contacting the first 3-D channel structure, and forming an opening extending into the S/D region, the opening having a depth greater than half of a height of the first 3-D channel structure; and forming a metallic plug in the opening, the metallic plug making electrical contact with the S/D region.

A semiconductor device includes; an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern. The semiconductor patterns includes a first semiconductor pattern and a second semiconductor pattern. The gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern. A width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.

A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

A biosensor includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a FET device in the semiconductor layer, an isolation layer over the first surface of the semiconductor layer, a dielectric layer over the isolation layer and the first surface of the semiconductor layer, and a pair of first electrodes and a pair of second electrodes over the dielectric layer and separated from each other. The isolation layer has a rectangular opening substantially aligned with the FET device. The rectangular opening has pair of first sides and a pair of second sides. An extending direction of the pair of first sides is perpendicular to an extending direction of the pair of second sides. The pair of first electrodes is disposed over the pair of first sides, and the pair of second electrodes is disposed over the pair of second sides.

Embodiments of present invention provide a static random-access-memory (SRAM). The SRAM includes a first and a second pull-down (PD) transistor having respectively a first and a fourth set of nanosheets of a first width; a first and a second pass-gate (PG) transistor having respectively a second and a fifth set of nanosheets of a second width; and a first and a second pull-up (PU) transistor having respectively a third and a sixth set of nanosheets of a third width, wherein the first width is wider than the second width, the second width is wider than the third width, the first set of nanosheets is substantially aligned with the second set of nanosheets at one side of the first and second sets of nanosheets, and the fourth set of nanosheets is substantially aligned with the fifth set of nanosheets at one side of the fourth and fifth sets of nanosheets.