The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N.sup.+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

A semiconductor device includes a gate structure that extends from a first surface into a semiconductor portion and that surrounds a transistor section of the semiconductor portion. A field plate structure includes a field electrode and extends from the first surface into the transistor section. A mesa section of the semiconductor portion separates the field plate structure and the gate structure. A contact structure includes a first portion directly adjoining the mesa section and a second portion directly adjoining the field electrode. The first and second portions include stripes and are directly connected to each other.

Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor device comprises a semiconductor substrate, a first ohmic contact and a second ohmic contact disposed over the semiconductor substrate, one or more coupling capacitors, and one or more capacitively-coupled field plates disposed over the semiconductor substrate between the first ohmic contact and the second ohmic contact. Each of the capacitively-coupled field plates is capacitively coupled to the first ohmic contact through one of the coupling capacitors, the coupling capacitor having a first terminal electrically connected to the first ohmic contact and a second terminal electrically connected to the capacitively-coupled field plate.

A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, the junction blocking region having a lower doping concentration. The junction blocking region extends between a pair of trench structures in cross-sectional view. The trench structures are provided in the semiconductor region and include at least one insulated electrode. In some embodiments, the semiconductor device further includes a first doped region disposed between the pair of trench structures. The semiconductor device may further include one or more features configured to improve operating performance. The features include a localized doped region adjoining a lower surface of a first doped region and spaced apart from the trench structure, a notch disposed proximate to the lower surface of the first doped region, and/or the at least one insulated electrode configured to have a wide portion adjoining a narrow portion.

A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).

A semiconductor device includes a layer having first and second surfaces, a first region including central and peripheral portions, and a second region on the first region. First trenches extend into the first surface and terminate within the first region in the central portion. Each first trench includes a first electrode and a gate electrode over the first electrode. The first and gate electrodes are spaced from the first and second regions by a first insulating layer. A second trench extends into the first surface and terminates within the first region in the peripheral portion. The second trench includes a second electrode and a third electrode over the second electrode. The second and third electrodes are spaced from the first and second regions by a second insulating layer. A fourth electrode overlies the first insulating layer in the central portion and the second insulating layer in the peripheral portion.

A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.