A semiconductor device includes a semiconductor substrate comprising a main surface and a gate electrode in a trench between neighboring semiconductor mesas, The gate electrode is electrically insulated from the neighboring semiconductor mesas by a dielectric layer. The semiconductor device further includes a conductor arranged, at least partially, between neighboring dielectric contact spacers. The conductor has a conductivity greater than a conductivity of the gate electrode, An interface between the conductor and the gate electrode extends along the gate electrode.

In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

A power semiconductor device includes a semiconductor substrate having a drift region, a gate electrode trench in the semiconductor substrate and a field electrode needle trench in the semiconductor substrate. The gate electrode trench extends into the drift region and includes a gate electrode. The gate electrode is arranged in the gate electrode trench and electrically insulated from the drift region by a gate dielectric layer arranged between the gate electrode and the drift region. The field electrode needle trench is laterally spaced from the gate electrode trench and extends into the drift region. The field electrode needle trench includes a field electrode arranged in the field electrode needle trench and electrically insulated from the drift region by a cavity formed between the field electrode and the drift region.

Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third trench gate electrodes located on both sides of the first trench gate electrode interposed therebetween. In each of a semiconductor layer located between the first and second trench gate electrodes and the semiconductor layer located between the first and third trench gate electrodes, a plurality of p.sup.+-type semiconductor regions are formed. The p.sup.+-type semiconductor regions are arranged along the extending direction of the first trench gate electrode in plan view to be spaced apart from each other.

The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.

Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.

Methods and systems provided. A system may include at least one camera at a camera location, wherein the at least one camera is configured to record one or more videos and one or more images. The system may further include a server. The server may be configure to download at least one image of the one or more images captured at the camera location. The server may also be configured to display the one or more downloaded images. Further, the server may also be configured to, in response to a user selecting a displayed image of the one or more displayed images, download a specific portion of the previously recorded one or more videos captured at the camera location.

A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.

Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, a semiconductor device includes a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET). The main-MOSFET includes a plurality of parallel main trenches, wherein the main trenches comprise a first electrode coupled to a gate of the main-MOSFET, and a plurality of main mesas between the main trenches, wherein the main mesas comprise a main source and a main body of the main-MOSFET. The semiconductor device also includes a sense-diode. The sense-diode includes a plurality of sense-diode trenches, wherein each of the sense-diode trenches comprises a portion of one of the main trenches, and a plurality of sense-diode mesas between the source-FET trenches, wherein the sense-diode mesas comprise a sense-diode anode that is electrically isolated from the main source of the main-MOSFET.