An apparatus includes a substrate of a first conductivity, an extended drain region of a second conductivity formed over the substrate, a body region of the first conductivity formed in the extended drain region, a source region of the second conductivity formed in the body region, a drain region of the second conductivity formed in the extended drain region, a first dielectric layer formed over the body region and the extended drain region, a second dielectric layer formed over the extended drain region, and between the first dielectric layer and the drain region, a first gate formed over the first dielectric layer, and a second gate formed over the second dielectric layer, wherein the second gate is electrically connected to the source region.

A semiconductor structure includes a substrate assembly and a semiconductor device. The semiconductor device is formed on the substrate assembly, and includes a body region, two active regions, and a butted body. The active regions are disposed at two opposite sides of the body region, and both have a first type conductivity. The body region and the active regions together occupy on a surface region of the substrate assembly. The butted body has a second type conductivity different from the first type conductivity, and is located on the surface region of the substrate assembly so as to permit the body region to be tied to one of the active regions through the butted body.

Semiconductor devices including a high-k field relief dielectric structure are described. The microelectronic device comprises a substrate including a body region and a drain drift region on the substrate, a gate dielectric layer extending over the body region and the drift region, a drain drift trench is formed by removal of silicon dioxide from a LOCOS silicon region, a high-k field relief dielectric structure laterally abutting the gate dielectric layer at a location in the drift region, and a gate electrode on the gate dielectric layer and the field relief dielectric layer. Increasing the dielectric constant of the field relief dielectric structure may improve channel hot carrier performance, improve breakdown voltage, and reduce the specific on resistance. A drain drift trench formed in a trench left after removal of silicon dioxide in a LOCOS region provides improved trench depth uniformity.

A semiconductor device can include: a substrate; a well region located in the substrate and having a first doping type; a body region located in the substrate and having a second doping type that is opposite to the first doping type; a source region located in the body region and having the first doping type; a drain region located in the well region and having the first doping type; an isolation structure located on the substrate and between the drain region and the source region; and a gate structure located on the isolation structure and including a first gate region and a second gate region, where the first gate region is of the first doping type, and the second gate region is of the second doping type.

A lateral diffused semiconductor device is disclosed, including: a substrate; a first isolation and a second isolation comprising at least portions disposed in the substrate to define an active area; a first drift region and a second drift region disposed in the active area, wherein the first drift region is disposed in the second drift region; a gate structure on the substrate; a source region in the first drift region; a drain region in the second drift region; and a ring-shaped field plate on the substrate, wherein the ring-shaped field plate surrounds at least one of the source and the drain region.

High voltage devices and methods for forming a high voltage device are disclosed. The high voltage device includes a substrate prepared with a device isolation region. The device isolation region defines a device region. The device region includes at least first and second source/drain regions and a gate region defined thereon. A device well is disposed in the device region. The device well encompasses the at least first and second source/drain regions. A primary gate and at least one secondary gate adjacent to the primary gate are disposed in the gate region. The at least first and second source/drain regions are displaced from first and second sides of the primary gate.

An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity 100 Ohm.cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.