A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.

A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side of the gate electrode, the trench being lined with a sidewall dielectric layer and filled with a bottom dielectric layer and a conductive layer above the bottom dielectric layer, the conductive layer being electrically connected to the gate electrode; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.

There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.

An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure. The source region (41) is located in the well region (34); the drain region (34) is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region (23) and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region (24) and a bottom-layer P-region which are butted vertically.

An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the drain region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the drain region.