A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the drain region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the drain region.

A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the gate electrode from a source region side toward a drain region side. The projection parts are arranged side by side along a second direction (direction orthogonal to a first direction along which the source region and the drain region are laid) in plan view. A plurality of openings is formed in the field oxide film. Each of the openings is located between projection parts adjacent to each other when seen from the first direction. The edge of the opening on the drain region side is located closer to the source region than the drain region. The edge of the opening on the source region side is located closer to the drain region than the side face of the gate electrode.

A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.

A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.

A semiconductor device includes a power element and a heat sensing element configured to detect a temperature of the power element. The power element includes lateral MOS transistors having drains and gate electrodes, two of the drains being shorter in length than the remaining drains and two of the gate electrodes being shorter in length than the remaining gate electrodes. The heat sensing element has a rectangular shape and is disposed between the two shorter drains and the two shorter gate electrodes to accurately detect the temperature of the power element.

A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.

A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.