A semiconductor device includes a transistor. The transistor includes a source region and a drain region disposed adjacent to a first main surface of a semiconductor substrate, a first gate electrode and a second gate electrode, the first gate electrode being disconnected from the second gate electrode. The transistor further includes a body region. The first gate electrode is adjacent to a first portion of the body region and the second gate electrode is adjacent to a second portion of the body region. The transistor further includes first trenches patterning the first portion of the body region into a first ridge, and second trenches patterning the second portion of the body region into a second ridge. The first gate electrode is arranged in at least one of first trenches, and the second gate electrode is arranged in at least one of the second trenches.

An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.

A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.

There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.

A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.

A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.

A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed by side and bottom surfaces of the first trenches; a first shallow trench isolation (STI) structure formed in each of the first trenches; a body region with the first doping type formed in semiconductor substrate at one side of the drift region; a gate structure formed over portions of the body region, the drift region and the first STI structure most close to the body region; a source region formed in the body region; and a drain region formed in the drift region at one side of the first STI structure most far away from the body region.

An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.