There is provided a method for manufacturing a nanostructure semiconductor light emitting device, including: forming a mask having a plurality of openings on a base layer; growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores; partially removing the mask such that side surfaces of the plurality of nanocores are exposed; heat-treating the plurality of nanocores after partially removing the mask; sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures, after the heat treatment; and planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed.

A light emitting diode chip includes: a first conductive type semiconductor layer disposed on a substrate; a mesa disposed on the first conductive type semiconductor layer and including an active layer and a second conductive type semiconductor layer; an insulation layer covering the first conductive type semiconductor layer and the mesa, the insulation layer including at least one first opening exposing the first conductive type semiconductor layer and a second opening disposed on the mesa; a first pad electrode disposed on the insulation layer and electrically connected to the first conductive type semiconductor layer through the first opening; and a second pad electrode disposed on the insulation layer and electrically connected to the second conductive type semiconductor layer through the second opening. The first opening of the insulation layer includes a first region covered by the first pad electrode and a second region exposed outside the first pad electrode.

A light-emitting element includes a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first contact electrode and a second contact electrode located on the light-emitting structure, and respectively making ohmic contact with the first conductive semiconductor layer and the second conductive semiconductor layer; an insulation layer for covering a part of the first contact electrode and the second contact electrode so as to insulate the first contact electrode and the second contact electrode; a first electrode pad and a second electrode pad electrically connected to each of the first contact electrode and the second contact electrode; and a radiation pad formed on the insulation layer, and radiating heat generated from the light-emitting structure.

Semiconductor LED layers are epitaxially grown on a patterned surface of a sapphire substrate. The patterned surface improves light extraction. The LED layers include a p-type layer and an n-type layer. The LED layers are etched to expose the n-type layer. One or more first metal layers are patterned to electrically contact the p-type layer and the n-type layer to form a p-metal contact and an n-metal contact. A dielectric polymer stress-buffer layer is spin-coated over the first metal layers to form a substantially planar surface over the first metal layers. The stress-buffer layer has openings exposing the p-metal contact and the n-metal contact. Metal solder pads are formed over the stress-buffer layer and electrically contact the p-metal contact and the n-metal contact through the openings in the stress-buffer layer. The stress-buffer layer acts as a buffer to accommodate differences in CTEs of the solder pads and underlying layers.

A light emitting diode chip including a substrate and a light emitting diode element layer is provided. The substrate has a growth surface and a plurality of microstructures on the growth surface. An area of the growth surface occupied by the microstructures is A1 and an area of the growth surface not occupied by the micro-structures is A2, such that A1 and A2 satisfy the relation of 0.1A2/(A1+A2)0.5. The light emitting diode element layer is disposed on the growth surface of the substrate.

A method for manufacturing a light emitting diode (LED) die includes providing an LED die including a substrate, an N type semiconductor layer, an active layer, and a P type semiconductor layer grown on the substrate in sequence. The N type semiconductor layer, the active layer, and the P type semiconductor layer are etched to define a plurality of recesses and a groove. An insulating layer to cover side surfaces of the recesses and the P type semiconductor layer is formed and a portion of the insulating layer is etched to define an opening to expose a top portion of the P type semiconductor layer. A pair of electrodes is formed and the LED die is cut along the groove to obtain an individual LED die.

The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

A light emitting diode (LED) includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, a first conductive layer disposed on a portion of the second semiconductor layer, a second conductive layer disposed on the second semiconductor layer, and an insulation layer including a first insulating layer and a second insulating layer disposed on the first insulating layer, and overlapping the first semiconductor layer, the second semiconductor layer, and the second conductive layer, in which the insulation layer has a first region having different thicknesses and a second region having a substantially constant thickness.

A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers.

A light emitting diode (LED) device includes a semiconductor nanowire core, and an In(Al)GaN active region quantum well shell located radially around the semiconductor nanowire core. The active quantum well shell contains indium rich regions having at least 5 atomic percent higher indium content than indium poor regions in the same shell. The active region quantum well shell has a non-uniform surface profile having at least 3 peaks. Each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley, and each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.