The present invention provides a method for testing performance of thin-film encapsulation. Through different combination designs of film layers, lateral water vapor intrusion paths of various thin films or encapsulation structures are formed, thereby obtaining a means to inspect a lateral water vapor and oxygen barrier capacity of thin films and provide a highly effective inspection means for encapsulation of display panels.

To provide a wavelength selection method or a plasma processing method to achieve accurate detection of residual thickness or etching amount, there is provided a plasma processing method, in which a processing object wafer is disposed within a processing chamber in the inside of a vacuum container, and plasma is generated by supplying a processing gas into the processing chamber and used to process a processing-object film layer beforehand formed on a surface of the wafer, and at least two wavelengths are selected from among wavelengths with large mutual information in emission of a plurality of wavelengths of plasma generated during processing of the processing-object film layer, and a temporal change in the emission of at least the two wavelengths is detected, and an endpoint of the processing of the film layer is determined based on a result of the detection.

A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.

A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

A semiconductor device capable of improving the quality of a pixel region, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device are to be provided. The present technology provides a semiconductor device that includes: a first substrate in which a pixel region including a pixel having a photoelectric conversion unit is formed; and a second substrate in which a logic circuit that processes a signal output from the pixel region is formed, the first substrate and the second substrate being stacked. In the semiconductor device, at least one of marks including a mark to be used in an exposure process during the manufacture of the semiconductor device and/or a mark to be used in an inspection process for the semiconductor device is formed in a first region that is a region between a first scribe region that is a peripheral portion of the first substrate and the pixel region and/or in a second region that is a region between a second scribe region that is a peripheral portion of the second substrate and a region corresponding to the pixel region in the second substrate.

A method of fabricating a semiconductor device may include designing a layout including first and second gate patterns, first and second dummy gate patterns, and third and fourth gate patterns sequentially arranged in a first direction; forming first to fourth sacrificial patterns and first and second dummy sacrificial patterns, which correspond to the first to fourth gate patterns and the first and second dummy gate patterns respectively, on a substrate using a photomask manufactured based on the layout; and performing an optical proximity correction on the layout. The optical proximity correction may include measuring distances between adjacent ones of the sacrificial and dummy sacrificial patterns in the first direction to provide measured distances, comparing a mean value of the measured distances with a mean value of target distances to obtain a first distance therebetween, and reducing a distance between the first and second dummy gate patterns by the first distance.

Apparatuses and methods with controlled resist poisoning in manufacturing semiconductor devices are described. An example apparatus includes a first structure and a second structure. The first structure includes a first conductive component and a second conductive component adjacent to one another. The second structure includes a third conductive component and a fourth conductive component adjacent to one another. The third and fourth conductive components correspond to the first and second conductive components respectively. A first distance between the first conductive component and the second conductive component is different from a second distance between the third conductive component and the fourth conductive component.

Methods and apparatus for processing a first substrate and a second substrate are provided herein. For example, a method of processing a substrate using extended spectroscopic ellipsometry (ESE) includes directing a beam from an extended spectroscopic ellipsometer toward a first surface of a first substrate and a second surface of a second substrate, which is different than the first substrate, determining in-situ ESE data from each of the first surface and the second surface during processing of the first substrate and the second substrate, measuring a change of phase and amplitude in determined in-situ ESE data, and determining one or more parameters of the first surface of the first substrate and the second surface of the second substrate using simultaneously complex dielectric function, optical conductivity, and electronic correlations from the measured change of phase and amplitude in the in-situ ESE data.

A defect observation method includes, as steps executed by a computer system, a first step of acquiring, as a bevel image, an image captured using defect candidate coordinates in a bevel portion as an imaging position by using a microscope or an imaging apparatus; and a second step of detecting a defect in the bevel image. The second step includes a step of determining whether there is at least one portion among a wafer edge, a wafer notch, and an orientation flat in the bevel image, a step of switching and selectively applying a defect detection scheme of detecting the defect from the bevel image from a plurality of schemes which are candidates based on a determination result, and a step of executing a process of detecting the defect from the bevel image in conformity with the switched scheme.

A semiconductor device layout structure includes: an active area layout layer including a plurality of first active area patterns, and at least one second active area pattern each connected to at least two of the plurality of first active area patterns; a drain contact layer configured to form a plurality of drain contact plugs and arranged on each first active area pattern; a source contact layer configured to form a source contact plug and arranged on the at least one second active area pattern; and a gate layer including a plurality of gate patterns extending in a first direction, the plurality of gate patterns being arranged over the plurality of first active area patterns at a position away from the drain contact layer and configured to form a plurality of gates.