A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.

The present disclosure provides a semiconductor manufacturing process control method and apparatus, a device, and a storage medium. The method includes: analyzing wafer lot information and determining a current product lot of a current product; obtaining historical measurement data within a specified period; when determining that the historical measurement data does not include first measurement data of the current product lot, if determining, based on preset configuration information, that the historical measurement data includes second measurement data of a target product lot, determining a target regulatory data based on the preset configuration information and the second measurement data; and controlling a production parameter of the current product based on the target regulatory data.

A critical dimension uniformity control method is provided. The method includes gathering a first CDU by a first critical dimension from a first wafer after being processed by a first surface process. The method includes determining a first calibration process based on the first CDU. The determining includes an intra dose correction step for correcting reticle-dependent deviation, a thru-slit dose sensitivity correction step for correcting time-dependent deviation, and an inter dose correction step for correcting process-dependent deviation. The method includes calibrating the first surface process by the first calibration process to determine a second surface process different from the first surface process.

A measurement device and method for a semiconductor structure are provided. The measurement device for the semiconductor structure includes a bearing platform, a clamping mechanism, and an image acquisition system. The clamping mechanism is installed on the bearing platform and includes a clamp disposed along a vertical direction. The clamp is configured to clamp the semiconductor structure such that the semiconductor structure is clamped with a to-be-measured surface facing a side. The image acquisition system is disposed by a side of the clamping mechanism, and is configured to acquire a three-dimensional morphology of the semiconductor structure from the side.

A test structure for a buried gate transistor includes a substrate, a first test contact located on one side of a first transistor contact, a second test contact located on one side of a second transistor contact, and a layer buried in the substrate, having a doping greater than or equal to 10.sup.18 cm.sup.−3, and having a face which is tangent to the buried part of the gate. A first insulation structure is disposed between the first test contact and the first transistor contact and a second insulation structure is disposed between the second test contact and the second transistor contact. The first and second test contacts each have an end connected to the buried layer.

A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

A method for controlling a critical dimension of a mask layer is described. The method includes receiving a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating a primary signal having the first primary parameter level, and transitioning the primary signal from the first primary parameter level to the second primary parameter level. The method further includes generating a secondary radio frequency (RF) signal having the first secondary parameter level, and transitioning the secondary RF signal from the first secondary parameter level to the second secondary parameter level. The method includes transitioning the secondary RF signal from the second secondary parameter level to the third secondary parameter level.

A semiconductor structure with backside through silicon vias (TSVs) is provided in the present invention, including a semiconductor substrate with a front side and a back side, multiple dummy pads set on the front side, multiple backside TSVs extending from the back side to the front side, wherein a number of the dummy pads are connected with the backside TSVs while other dummy pads are not connected with the backside TSVs, and a metal coating covering the back side and the surface of backside TSVs and connected with those dummy pads that connecting with the backside TSVs.

To provide a technique capable of quantitatively grasping a change in three-dimensional shape including a cross-sectional shape of a pattern within a surface of a wafer or between wafers in a non-destructive manner before cross-sectional observation. A processor system of a semiconductor inspection system acquires images captured by an electron microscope (SEM) for a sample (S102), calculates, for a reference region defined on a surface of the sample, first feature data corresponding to each of a plurality of locations in the reference region from the captured image (S103A), calculates a first statistical value based on the first feature data at the plurality of locations (S103B), calculates, for each of a plurality of evaluation regions defined as points or regions on the surface of the sample in correspondence with the reference region, second feature data corresponding to each of one or more locations in the evaluation region from the captured image, as feature data of the same type as the first feature data (S104A), and converts the second feature data using the first statistical value to obtain second feature data after conversion (S105).

Systems and methods for brightfield inspection of a circular rotating wafer are provided. A method includes: acquiring a plurality of images of a circular wafer, that is rotating, by using a plurality of line cameras; obtaining a plurality of synchronized images, based on the plurality of images, by synchronizing a motion of the circular wafer, that is rotating, with at least one line camera from among the plurality of line cameras; obtaining a single wafer map by integrating together the plurality of synchronized images; obtaining an in-focus image of the single wafer map while the circular wafer is moving; and performing brightfield inspection of the circular wafer based on the in-focus image of the single wafer map.