Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having an active region and an isolation region. The semiconductor structure includes gate stacks on the substrate that extend over the active region and the isolation region. The semiconductor structure includes a gate spacer on sidewalls of the gate stacks. The semiconductor structure includes an interlevel dielectric (ILD) layer over the substrate and implanted with one or more dopants, the ILD layer having a top implanted portion over a bottom nonimplanted portion. The top implanted portion seals an air gap between a sidewall of the ILD layer and the gate spacer.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a nanostructure over the fin. The semiconductor device structure includes a gate stack wrapping around an upper portion of the fin and the nanostructure. The semiconductor device structure includes an inner spacer between the fin and the nanostructure. The semiconductor device structure includes a film in the inner spacer. A first dielectric constant of the film is lower than a second dielectric constant of the inner spacer. The semiconductor device structure includes a low dielectric constant structure in the film.

In an embodiment, a device includes: a first fin extending from a substrate; a second fin extending from the substrate; a gate spacer over the first fin and the second fin; a gate dielectric having a first portion, a second portion, and a third portion, the first portion extending along a first sidewall of the first fin, the second portion extending along a second sidewall of the second fin, the third portion extending along a third sidewall of the gate spacer, the third portion and the first portion forming a first acute angle, the third portion and the second portion forming a second acute angle; and a gate electrode on the gate dielectric.

An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.

A method includes providing a substrate, an isolation structure, and a fin extending from the substrate and through the isolation structure. The fin includes a stack of layers having first and second layers that are alternately stacked and have first and second semiconductor materials respectively. A topmost layer of the stack is one of the second layers. The structure further has a sacrificial gate stack engaging a channel region of the fin. The method further includes forming gate spacers and forming sidewall spacers on sidewalls of the fin in a source/drain region of the fin, wherein the sidewall spacers extend above a bottom surface of a topmost one of the first layers. The method further includes etching the fin in the source/drain region, resulting in a source/drain trench; partially recessing the second layers exposed in the source/drain trench, resulting in gaps; and forming dielectric inner spacers inside the gaps.

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.

A device includes a bipolar transistor. The bipolar transistor includes: a collector region, a base region, and an emitter region. A first metallization is in contact with the emitter region, a second metallization is in contact with the base region, and a third metallization is in contact with the collector region. A first connection element is coupled to the first metallization and has dimensions, in a plane of the interface between the first metallization and the connection element, greater than dimensions of the first metallization. A second connection element is coupled to the second metallization and passes through spacers, which at least partially cover the second metallization, surrounding the emitter region. A third connection element is coupled to the third metallization and passes through spacers, which at least partially cover the third metallization, surrounding the base region.

A method includes providing a workpiece. The workpiece includes a substrate, a fin protruding from the substrate, and a dummy gate structure over the fin. The method further includes performing an oxidizing process to exposed surfaces of the fin and the dummy gate structure to form an oxide layer thereon, removing the oxide layer to expose an unoxidized top surface and sidewalls of the fin and unoxidized sidewalls of the dummy gate structure, epitaxially growing a cap layer on the unoxidized top surface and sidewalls of the fin and the unoxidized sidewalls of the dummy gate structure, forming a source/drain feature on the fin, and replacing the dummy gate structure with a metal gate structure.

A semiconductor device includes a substrate having a fin element extending therefrom. In some embodiments, a gate structure is formed over the fin element, where the gate structure includes a dielectric layer on the fin element, a metal capping layer disposed over the dielectric layer, and a metal electrode formed over the metal capping layer. In some cases, first sidewall spacers are formed on opposing sidewalls of the metal capping layer and the metal electrode. In various embodiments, the dielectric layer extends laterally underneath the first sidewall spacers to form a dielectric footing region.