A method of fabricating a unit cell of a focal plane array includes providing an integrated circuit substrate, depositing a proximal portion of a dielectric layer on the substrate, and etching a plurality of recess structures into the dielectric layer. Each of the plurality of recess structures defines a partial via and includes sidewalls that extend from the first surface to a bottom portion of the respective recess structure. The method also includes forming a capacitor structure, depositing a distal portion of the dielectric layer on the capacitor structure and a region of the proximal portion of the dielectric layer, forming a plurality of vias passing to the capacitor structure, forming a metal layer, and forming a detector overlying the metal layer. The plurality of vias are positioned between the capacitor structure and the metal layer and electrically connect the capacitor structure to the metal layer.

Disclosed herein is a semiconductor device including first and second capacitor structures formed to be spaced apart from each other on a semiconductor substrate, wherein the first capacitor structure includes a first trench formed in the semiconductor substrate, first, second, and third electrode layers disposed in the first trench, and first, second, and third dielectric layers disposed in an interlaced structure with the semiconductor substrate and the first to third electrode layers, the second capacitor structure includes a second trench formed in the semiconductor substrate, fourth, fifth, and sixth electrode layers disposed in the first trench, and fourth, fifth, and sixth dielectric layers disposed in an interlaced structure with the semiconductor substrate and the fourth to sixth electrode layers, and a connection blocking area formed between the first and second capacitor structures to block connections between elements constituting the first capacitor structure and elements constituting the second capacitor structure.

Disclosed herein are IC devices with fishbone capacitor structures. An example capacitor structure includes a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode, wherein the first capacitor electrode is a first line with protrusions on a side of the first line, the second capacitor electrode is a second line with protrusions on a first side of the second line and protrusions on a second side of the second line, the third capacitor electrode is a third line with protrusions on a side of the third line, the protrusions on the side of the first line and the protrusions on the first side of the second line form a first interdigitated capacitor structure, and the protrusions on the side of the third line and the protrusions on the second side of the second line form a second interdigitated capacitor structure.

Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

A capacitor includes a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14, a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor located on a substrate, a dielectric layer on the transistor, and a capacitor in the dielectric layer and including a bottom capacitor plate connected to a source region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.

A capacitor device and a manufacturing method thereof are disclosed in the present invention. The capacitor device includes pad structures, bottom electrodes, a top electrode, and a dielectric layer. The bottom electrodes are disposed on the pad structures, respectively. The top electrode is disposed on the bottom electrodes. The dielectric layer is disposed between the top electrode and the bottom electrodes. The top electrode includes at least one void. The manufacturing throughput of the manufacturing method of the memory device may be enhanced accordingly.

A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.

A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.